Signals and Connections for x32 Dual Channel LPDDR4 SDP without ECC

UltraScale Architecture PCB Design User Guide (UG583)

Document ID
UG583
Release Date
2023-11-14
Revision
1.27 English

The required signals for a x32 dual channel LPDDR4 SDP without ECC interface are shown in Table: Signal Connection Matrix for x32 Dual Channel LPDDR4 SDP without ECC. The table shows which FPGA memory interface signals connect to which pins on the LPDDR4 device, along with any required termination.

Table 2-37:      Signal Connection Matrix for x32 Dual Channel LPDDR4 SDP without ECC

FPGA Pins

LPDDR4 Pins

PCB Termination at Far End

Clock Signals

CK0_P
CK0_N

CK_t_A
CK_c_A

None

CK1_P
CK1_N

CK_t_B
CK_c_B

None

Address and Command Signals

A[5:0]

CA[5:0]_A

None

A[15:10]

CA[5:0]_B

None

Control Signals (CKE, CS, and ODT (1))

CKE0

CKE_A
CKE_B

160W to VDDQ/160W to GND

CS0

CS_A CS_B

None

 

ODT_CA_A

Direct connect to VDD2

 

ODT_CA_B

Direct connect to VDD2

Data Signals

DQ[15:0]

DQ[15:0]_A

None

DQ[31:16]

DQ[15:0]_B

None

DM0

DMI0_A

None

DM1

DMI1_A

None

DM2

DMI0_B

None

DM3

DMI1_B

None

DQS0_P/
DQS0_N

DQS0_t_A/
DQS0_c_A

None

DQS1_P/
DQS1_N

DQS1_t_A/
DQS1_c_A

None

DQS2_P/
DQS2_N

DQS0_t_B/
DQS0_c_B

None

DQS3_P/
DQS3_N

DQS1_t_B/
DQS1_c_B

None

Reset

RESET_N

RESET_n

4.7 kW to GND

-

ZQ0

240W to VDDQ

ZQ

-

240W to GND

Notes:

1.The FPGA ODT pins should be left unconnected. The ODT pin(s) of the memory device should be directly connected as specified in this table.

2.The ZQ pin on the LPDDR4 devices should be tied to VDDQ through a 240W resistor.

3.Actual signal list might vary based on configuration.