1.Review footprint compatibility, including banks that are bonded vs. unbonded.
2.Review package dimensions, including height and overhang.
3.Review I/O and transceiver Quad numbering and locations.
4.Review HPIO to HRIO and HRIO to HPIO migration.
5.Review GTH to GTY and GTY to GTH transceiver migration.
6.Review the super logic region (SLR) boundaries.
7.Review monolithic to stacked silicon migration as it pertains to configuration banks.
8.Review memory interface locations to maintain bank grouping.
9.Review DCI cascade and internal VREF requirements.
10.Review system monitor requirements and pin differences.
11.Review decoupling capacitor requirements.
12.Review PCI Express® requirements and block locations.
13.Review integrated 100G Ethernet requirements and block locations.
14.Review Interlaken requirements and block locations.
15.Review power supply and thermal requirements.
16.Review pin flight time differences between devices.