In some cases, one or more I/O/PSIO banks in an FPGA are not used (for example, when an FPGA has far more I/O pins than the design requires). In these cases, it might be desirable to leave the bank’s associated VCCO pins unconnected, as it can free up some PCB layout constraints (less voiding of power and ground planes from via antipads, less obstacles to signals entering and exiting the pinout array, more copper area available for other planelets in the otherwise used plane layer).
Leaving the VCCO pins of unused I/O/PSIO banks floating reduces the level of ESD protection on these pins and the I/O pins in the bank. For maximum ESD protection in an unused bank, all VCCO pins in that bank should be connected together to the same potential, whether that be a valid VCCO voltage, or a floating plane. I/O/PSIO pins are also recommended to be connected to the same potential as VCCO, or they can be left floating. If using SYSMON VAUX inputs to monitor voltages on the board, it is not recommended to ground VCCO pins of any I/O/PSIO banks because this can interfere with ADC accuracy. In this case, tie the VCCO of all unused I/O banks to an existing I/O/PSIO voltage plane that is applicable to the bank type of the unused bank.