A new feature for DDR4 memories in the Memory Interface Generator (MIG) tool allows users to prepare for migration from one device to another by specifying the differences in address/command/control pin delays from the initial device to the migrated device.
To enable the DDR4 migration feature in the MIG tool, select the Enable Migration checkbox in the Advanced Options tab, as shown in This Figure.
After enabling migration, select the Migration Options tab and enter the relevant skew values as outlined in UltraScale Architecture FPGAs Memory IP Product Guide (PG150) [Ref 13] between the two devices (This Figure). The pin delays can be found via Example 1: Obtaining Pin Flight Times During I/O Planning or Example 2: Obtaining Pin Flight Times after Synthesis. The delay values entered should be positive and between 0 and 75 ps.
