Zynq\ UltraScale+\ RFSoC Device Organization and PCB Design Overview

UltraScale Architecture PCB Design User Guide (UG583)

Document ID
UG583
Release Date
2023-11-14
Revision
1.27 English

To assist with keeping sensitive analog circuitry as separate as possible from digital circuitry, the Zynq\ UltraScale+\ RFSoC is sectioned on the die such that the Analog-to-Digital (ADC) and Digital-to-Analog (DAC) portions are partitioned away from each other and from digital logic. This Figure shows the floorplan of the XCZU28DRFFVE1156 RFSoC with the ADC and DAC signals and pins located separately from the digital programmable logic (PL).

Figure 3-2:      XCZU28DR-FFVE1156 Floorplan

X-Ref Target - Figure 3-2

X18569-ZCZU28DR-FFVE1156-floorplan.jpg

The overall goal of a successful PCB design is to keep the analog portions as isolated as possible from both outside electromagnetic (EM) interference and potential on-chip EM interference by the digital logic and analog circuits.