For Zynq UltraScale+ MPSoC designs with component interfaces, connect the PS_DDR_ALERT_N pin to the ALERT_N pins of the DDR4 devices in fly-by routing and terminate to VDD with a 50W pull-up resistor. For Zynq UltraScale+ MPSoC designs with DIMMs, connect the PS_DDR_ALERT_N pin to the ALERT_N pin of the connector. For PL-based designs, the controller does not generate an ALERT_N pin but the DDR4 component ALERT_N signals must be connected together via fly-by routing and terminated to VDD with a 50W pull-up resistor. For PL-based designs with DIMMs, leave the ALERT_N pin floating at the connector. The ALERT_N signal does not have any skew or length matching requirements.
Table: DDR4 SDRAM Fly-by Impedance, Length, and Spacing Guidelines for Address, Command, and Control Signals shows the DDR4 SDRAM fly-by impedance, length, and spacing guidelines for address, command, and control signals.
|
Parameter |
L0 |
L1 |
L2 |
L3 |
L4 |
Units |
|---|---|---|---|---|---|---|
|
Trace type |
Stripline |
Stripline |
Stripline |
Stripline |
Stripline |
– |
|
Single-ended impedance Z0 |
50±10% |
36±10% |
50±10% |
50±10% |
39±10% |
W |
|
Trace width |
4.0 |
7.0 |
4.0 |
4.0 |
6.0 |
mil |
|
Trace length |
0.0~4.0 |
0.0~0.1 |
0.35~0.75 |
0~1 |
inches |
|
|
Spacing in address, command, and control signals (minimum) |
4.0 |
8.0(2) |
4.0 |
8.0 |
8.0 |
mil |
|
Spacing to clock signals (minimum) |
8.0 |
20 |
8.0 |
20 |
20 |
mil |
|
Spacing to other group signals (minimum) |
8.0 |
30 |
30 |
30 |
30 |
mil |
|
Maximum PCB via count |
7 |
– |
||||
|
Notes: 1.See item 2 in General Memory Routing Guidelines. 2.If greater than 1.5 inches is needed in the breakout area, change L1 spacing to 12.0. |
||||||
For DDR4 SDRAM clamshell topology, an alternating fly-by topology is recommended for control/address/command signals. The alternating layer routing properly balances the signal loads at each memory device. As depicted in This Figure with the FPGA located at the top layer, the inner layer routing to top layer devices 1, 3, 5, 7, and 9 is closer to the top layer, while the inner layer routing to bottom layer devices 2, 4, 6, and 8 is closer to the bottom layer.
Note: The end-termination resistor can be located on either the top or bottom layer.
DDR4 SDRAM clamshell topology utilizes two individual chip select (CS) signals, one for the top layer DRAMs, and one for the bottom layer DRAMs. Those signals should be routed as in the standard fly-by topology as defined in This Figure and Table: DDR4 SDRAM Fly-by Impedance, Length, and Spacing Guidelines for Address, Command, and Control Signals.
Table: DDR4 SDRAM Clamshell Impedance, Length, Width, and Spacing Guidelines for Address/Command/Control Signals shows the DDR4 SDRAM clamshell impedance, length, and spacing guidelines for address, command, and control signals. Note the extra length of the L2 segment.
|
Parameter |
L0 FPGA Breakout |
L1 |
L2 |
L3 |
L4 |
L5 |
L6 VTT Stub |
Units |
|---|---|---|---|---|---|---|---|---|
|
Layer (recommended) |
Upper inner |
Upper inner |
Lower inner |
Upper inner |
Top |
Bottom |
Bottom |
|
|
Impedance Z0 |
50 |
50 |
50 |
50 |
50 |
50 |
39 |
W |
|
Length |
0.0~1.5(1) |
0.0~4.0 |
L3+0.2 |
0.45~0.85 |
For mirrored case, L4 = L5; for non- mirrored case, make as short as possible |
£0.95 |
inch |
|
|
Width |
4.0 |
4.0 |
4.0 |
4.0 |
4.0 |
4.0 |
6.0 |
mil |
|
Spacing within group |
4.0 |
8.0(1) |
8.0 |
8.0 |
8.0 |
8.0 |
8.0 |
mil |
|
Spacing to clocks |
8.0 |
20 |
20 |
20 |
20 |
20 |
20 |
mil |
|
Spacing to other groups |
8.0 |
30 |
30 |
30 |
30 |
30 |
30 |
mil |
|
Notes: 1.If greater than 1.5 inches is needed in the breakout area, change L1 spacing to 12.0. |
||||||||
IMPORTANT: Add as many ground vias as possible to help avoid crosstalk issues. See Item 20 in General Memory Routing Guidelines.