config_compile_simlib - 2023.2 English

Description

Configure third-party simulator options for use by the compile_simlib command.

The AMD Vivado™ Design Suite has a pre-defined configuration file for the compile_simlib command, with compilation options defined for supported third-party simulators, languages, and libraries. The config_compile_simlib command is provided to let you change the configuration options for specific combinations of simulator, language, and library.

Use the config_compile_simlib command without any arguments to return all current configuration options.

Arguments

-cfgopt <arg> - (Optional) Specify the configuration options for a specific third party simulator, language, and library combination. The -cfgopt argument is specified as a string made up of four parts in the following form.

{<simulator>.<language>.<library>.<options> }

where,

• <simulator> - Specify the third-party simulator to configure options for. Refer to the compile_simlib command for currently supported versions of third-party simulators. Valid values are modelsim, questa, xcelium, vcs, riviera, activehdl
• <language> - Specify the language to set the simulation options for. Valid values are verilog, vhdl, g++, gcc, <compiler>
• <library> - Specify the library to compile. Valid values are axi_bfm, ieee, simprim, xpm, xilinx_vip, std, synopsys, unisim, secureip, vl, global, <ip>
• <options> - Configuration options specific to the simulator, language, and library specified. The following are the default compilation options available for different <simulator>.<language>.<library> combinations.
  • modelsim: -quiet, +define+XIL_TIMING, -93 (vhdl), -source (simprim, unisim)
  • questa: -quiet, +define+XIL_TIMING, -93 (vhdl), -source (simprim, unisim)
  • - xcelium: -MESSAGES, -NOLOG, -DEFINE XIL_TIMING, -v93 (vhdl), -RELAX (vhdl)
  • - vcs: -sverilog (verilog), -nc, +v2k (simprim, unisim), +define+XIL_TIMING
  • - riviera: -v2k5 (verilog), +define+XIL_TIMING, -93 (vhdl), -nowarn ELAB1_0026 (vhdl)
  • - activehdl: -v2k5 (verilog), +define+XIL_TIMING, -93 (vhdl), -nowarn ELAB1_0026 (vhdl)
  Note: Refer to the third-party simulator documentation for other compilation options that may be supported.

{<simulator>.<language>.<library>}

-simulator <arg> - (Optional) This option acts as a filter to return only the configuration options associated with the specified simulator. Refer to the -cfgopt option for a list of valid simulator values.

-reset - (Optional) Restore all configuration settings to the factory default value.

Examples

The following example prints the available configurations for the Questa simulator:

config_compile_simlib -simulator questa

The following example configures the compilation options for the verilog unisim library when compiling for ModelSim simulator:

config_compile_simlib -cfgopt {modelsim.verilog.unisim: -O4}

The following example configures the compilation options for the verilog synopsys and verilog simprim library when compiling for Questa simulator:

config_compile_simlib -cfgopt {questa.verilog.synopsys: -quiet} \
-cfgopt {questa.verilog.simprim:-source +define+XIL_TIMING}

The following example configures the compilation options for all vhdl based libraries when compiling for Xcelium simulator:

config_compile_simlib -cfgopt {xcelium.vhdl.global: -MESSAGES}

The following example configures the compilation options for the hdcp_v1_0_3 IP library when compiling for VCS simulator:

config_compile_simlib -cfgopt {vcs.vhdl.hdcp_v1_0_3: -MESSAGES}

The following example returns the current value of the configured option for the Riviera verilog xpm library:

config_compile_simlib -cfgval {riviera.verilog.xpm}

See Also

• compile_simlib