create_bd_cell - 2023.2 English

Description

Add a cell from the AMD Vivado™ Design Suite catalog to the current subsystem design, create a new hierarchical module to add to the subsystem design, or create a new module by referencing the module definition from an HDL source file.

When adding an IP core from the catalog, the -vlnv argument is required.

When creating a new hierarchical block design module, the -type hier argument is required.

When creating a block design module that references an RTL module or entity declaration the -type module argument is required, as well as -reference. The module reference feature lets you add a module definition from an RTL file (Verilog or VHDL) into the block design. The source file containing the module definition must be added to the project, or read into the design before creating a module reference. Refer to the Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994) for more information on referencing modules.

This command returns the name of the newly created cell object, or returns nothing if the command fails.

Arguments

-vlnv <arg> - (Required) This option is required for -type IP (the default), or optional for -type hier. Specify the Vendor:Library:Name:Version attribute of the cell to add from the IP integrator catalog. The VLNV attribute identifies the object in the IP integrator catalog. This argument is not needed when creating a new hierarchical module.

-type [ IP | hier | container | module ] - (Optional) Specify the cell as being:

• IP: IP from the Vivado IP catalog. This is the default type of block design cell created, but requires the use of the -vlnv option.
• hier: A new empty hierarchical block design module to add to, and populate in the current design.
• container: A block design container referenced from a BD file loaded in the source fileset. This requires the use of the -reference option.
• module: A hierarchical module referenced from a Verilog or VHDL file loaded in the source fileset. This requires the use of the -reference option.

-reference <arg> - (Optional) Specifies the module name to reference from a loaded RTL design source file.

<name> - The name of the IP cell or hierarchical module to add to the current IP subsystem design.

Examples

This example adds an AXI FIFO core from the IP integrator catalog to the current subsystem design, with the specified name:

create_bd_cell -vlnv xilinx.com:ip:axi_fifo_mm_s:4.0 axi_fifo_1

This example creates a new block design container in the block design, referencing the specified module definition from a previously loaded BD source file:

set bdc [ create_bd_cell -type container -reference hier_0 bdc ]

This example creates a new module in the block design, referencing the specified module definition from a previously loaded RTL source file:

create_bd_cell -type module -reference rtlRam rtlRam_0

This example creates a new hierarchical module, myModule1, and moves the AXI FIFO from the prior example into the new module. myModule1 is set as the current instance in the subsystem design, and a new module is created, myModule2, which is added to the current instance. Finally the current instance is reset to point to the top-level of the subsystem design:

create_bd_cell -type hier myModule1
/myModule1
move_bd_cells /myModule1 [get_bd_cells /axi_fifo_1]
/myModule1
current_bd_instance /myModule1
/myModule1
create_bd_cell -type hier myModule2
/myModule1/myModule2
current_bd_instance
/

See Also

• copy_bd_objs
• current_bd_instance
• move_bd_cells
• update_module_reference