export_simulation - 2023.2 English

Vivado Design Suite Tcl Command Reference Guide (UG835)
Document ID
UG835
Release Date
2023-10-18
Version
2023.2 English

Export a script and associated data files (if any) for driving standalone simulation using the specified simulator.

Syntax

export_simulation [‑simulator <arg>] [‑of_objects <args>] [‑step <arg>]
    [‑ip_user_files_dir <arg>] [‑ipstatic_source_dir <arg>]
    [‑lib_map_path <arg>] [‑install_path <arg>] [‑gcc_install_path <arg>]
    [‑script_name <arg>] [‑directory <arg>] [‑runtime <arg>]
    [‑define <args>] [‑generic <args>] [‑include <args>]
    [‑more_options <args>] [‑single_step] [‑use_ip_compiled_libs]
    [‑absolute_path] [‑export_source_files] [‑generate_hier_access] [‑exec]
    [‑report_ip_status] [‑force] [‑quiet] [‑verbose]

Usage

Name Description
[-simulator] Target simulator (all|xsim|modelsim|questa|xcelium |vcs|riviera|activehdl). Default:all
[-of_objects] Export simulation script for the specified object (IP/BD)
[-step] Write script for the specified step (Values: 'compile', 'elaborate', 'simulate'). For -single_step specify 'simulate' value.
[-ip_user_files_dir] Directory path to the exported IP/BD files (static, dynamic, data)
[-ipstatic_source_dir] Directory path to the exported IP/BD static files
[-lib_map_path] Compiled simulation library directory path
[-install_path] Simulator installation directory path
[-gcc_install_path] GNU compiler installation directory path for the g++/gcc executables
[-script_name] Output script filename (Default:<ip>)
[-directory] output directory path for the generated script
[-runtime] Simulation run time (default:full simulation run or until a logical break or finish condition)
[-define] Verilog defines
[-generic] Vhdl generics
[-include] Include directory path(s)
[-more_options] Additional options for simulator tools
[-single_step] Write single-step script (supported simulators: xcelium)
[-use_ip_compiled_libs] Reference pre-compiled IP simulation library
[-absolute_path] Make all file paths absolute
[-export_source_files] Copy IP/BD source files to the output directory
[-generate_hier_access] Extract path for hierarchical access simulation
[-exec] Execute generated script
[-report_ip_status] Check IP/BD generation status for 'not generated' or 'stale' simulation targets
[-force] Overwrite previous files
[-quiet] Ignore command errors
[-verbose] Suspend message limits during command execution

Categories

ToolLaunch

Description

Export a simulation script file for the target simulator. The generated script will contain simulator tool commands for compiling, elaborating, and simulating the design.

The command retrieves the simulation compile order of specified object and export this information in a shell script, .do or .prj file.

The specified object can be either a simulation fileset, IP or a BD (Block Design). If the object is not specified, then this command will generate a script for the active simulation top in the current simulation fileset source hierarchy.

By default, the design source file and include directory paths in the compiler command line will be set in relative format. To make these paths absolute, specify the -absolute_path switch. The command will also copy data files (if any) from the fileset, IP or a BD to the output directory. If the design contains verilog sources, then the generated script will also copy the glbl.v file from the Vivado™ software installation area to the output directory.

Note: In order to perform simulation with the generated script, the Xilinx simulation library must be compiled first using compile_simlib Tcl command. The compiled library directory path then must be specified when generating the script. The generated script will automatically include the setup files for the target simulator from the compiled library directory.
Note: If a design contains IP/BD sources, these sources must be generated first before exporting the script. The command does not generate output products of these sources, but checks for the status of these sources and print message accordingly.

This command returns nothing.

Arguments

-simulator <arg> - (Required) Specify the target simulator name for which the simulation script needs to be generated. The valid simulator names are xsim, modelsim, questa, xcelium, vcs, riviera, and activehdl. If this option is not specified, then the command will generate the script for all simulators.

-of_objects <arg> - (Optional) Specify the target object for which the simulation script needs to be generated. The target object can be a simulation fileset (simset), an IP, or BD source. If this option is not specified, then the command will generate scripts for the current simulation fileset.

Note: The -of_objects option requires objects to be specified using the get_files, get_ips, current_fileset, or current_fileset -simset commands rather than specifying objects by name. In addition, -of_objects cannot be used with a search <pattern>.

-ip_user_files_dir <arg> - (Optional) Specify the directory path to the extracted design files for the generated IP/BD source. This is generally the sub-directory named <project>.ip_user_files in the project directory structure.

-ipstatic_source_dir <arg> - (Optional) Specify the directory path to the exported IP/BD generated static source files. This is generally the sub-directory named <project>/project.ip_user_files in the project directory structure. For a managed-IP project, the default path is ip_user_files/ipstatic.

-lib_map_path <arg> - (Optional) Specify directory path to the pre-compiled simulation library for the specified simulator. The simulation library is compiled using compile_simlib Tcl Command (Please see the header section in the generated script for more information). If this switch is not specified, then the generated script will not reference the pre-compiled simulation library and the static IP files will be compiled locally.

  • To specify a pre-compiled library location, if you specified a simulator name with the -simulator switch, then use the following syntax:
    -lib_map_path <compiled-library>
  • To specify multiple pre-compiled library locations, if you specified the all value with the -simulator switch, then use the following syntax:
    -lib_map_path [list {<simulator>=<compiled-library>} {<simulator>=<compiled-library>} ... {<simulator>=<compiled-library>}]
    Where <simulator> is the name of the simulator and <compiled-library> is the path to the simulation library compiled for the simulator specified with <simulator>.

-gcc_install_path <arg> - (Optional) Specify the directory path to the GNU executables for the target simulator. This option is required for designs that contain SystemC, C++, or C sources.

-script_name <arg> - (Optional) Specify the name of the generated script. Default name is <simulation_top>.sh. If the -of_objects switch is specified, then the default syntax of the script will be as follows:

 -------------------------------------------------------------
     Object Type                            Script Name
    -------------------------------------------------------------
    -of_objects [current_fileset -simset]   <simulation_top>.sh
    -of_objects [get_ips <ip>]              <ip_name>.sh
    -of_objects [get_files <ip>.xci]        <ip_name>.sh
    -of_objects [get_files <name>.bd]       <bd_name>.sh
    -------------------------------------------------------

-directory <arg> - (Optional) Specify the directory path where the script file needs to be generated. By default, the script will be generated in the export_sim/<simulator> directory.

-runtime <arg> - (Optional) Specify the simulation run time. If this option is not specified, then the simulation will run for infinite time or until a logical break or finish condition.

-define <arg> - (Optional) Specify the Verilog defines applicable for the current design. The syntax for specifying the defines is:

-define [list {<variable[=value]} ... [{<variable[=value]>}]]

-generic <arg> - (Optional) Specify the VHDL generics applicable for the current design. The syntax for specifying the generic variables is:

-generic [list {<variable[=value]} ... [{<variable[=value]>}]]

-include <arg> - (Optional) Specify include directory paths for verilog include files in the design. The syntax for specifying the include file directory paths is:

-include [list {<include-directory} ... [{<include-directory>}]]
-more_options <arg> - (Optional) Specify additional switches/args for the simulator tools that need to be added when executing the script. The syntax for specifying the switches/args is:
-more_options [list {<simulator>.<step>.<tool>:<list of switches/args>} {<simulator>.<step>.<tool>:<list of switches/args>} ... {<simulator>.<step>.<tool>:<list of switches/args>}]
where,
  • <simulator> : Name of the simulator
  • <step> : Name of the step (compile, elaborate, simulate)
  • <tool> : Name of the simulator tool (xvlog, vcom, vcs, etc.)

-use_ip_compiled_libs - (Optional) Reference precompiled IP static library during compilation. The IP static source will not be compiled but instead it is compiled version will be referenced during elaboration. This switch requires -ip_user_files_dir and the -ipstatic_source_dir switches as well for generating scripts using pre-compiled IP.

-absolute_path - (Optional) Specify this option to make the source and include directory paths into absolute format in the generated script file. By default, all paths are written relative to the script output directory.

-export_source_files - (Optional) Specify this option to copy the design, generated IP/BD, and data sources to the <simulator>/srcs sub-directory. If the -of_objects specifies an IP or BD source, then the source files for these objects will be copied to the <IP/BD>/<simulator>/srcs sub-directory. The source and include file paths in the generated script will be set relative to the srcs directory (the file paths can be made absolute using the -absolute_path switch).

-generate_hier_access - (Optional) Specify this option to extract the path information for the hierarchical access simulation flow.

-32bit - (Optional) Specify this option to perform 32-bit simulation. If this option is not specified then by default a 64-bit option will be added to the simulation command line as applicable.

-force - (Optional) Overwrite an existing script file of the same name. If the script file already exists, is command returns an error unless the -force argument is specified.

-quiet - (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.
Note: Any errors encountered on the command-line, while launching the command, will be returned. Only errors occurring inside the command will be trapped.
-verbose - (Optional) Temporarily override any message limits and return all messages from this command.
Note: Message limits can be defined with the set_msg_config command.

Examples

Generate a simulation script for the clk_core IP in a managed-IP project for the questa simulator.

 export_simulation \
     -simulator questa \
     -of_objects [get_ips clk_core] \
     -directory proj/test_ip_questa \
     -ip_user_files_dir managed_ip_project/ip_user_files_dir \
 i   -ipstatic_source_dir managed_ip_project/ip_user_files_dir/ipstatic \
     -lib_map_path /design/compiled_libs/questa/lib \
     -use_ip_compiled_libs

Generate a simulation script named tb_design.sh in test_xsim directory for the current simulation fileset with the top set to tb_design for project project_1/project_1.xpr for the xsim simulator. Use the pre-compiled IP static library from the Vivado installation.

 export_simulation \
      -simulator xsim \
      -directory test_xsim \
      -ip_user_files_dir project_1/project_1.ip_user_files_dir \
      -ipstatic_source_dir project_1/project_1.ip_user_files_dir/ipstatic \
      -use_ip_compiled_libs

Generate a simulation script for project project_1/project_1.xpr for the modelsim simulator. Use the pre-compiled IP static library from the /design/compiled_libs/modelsim/lib directory and export the IP/BD source files to the proj/test_modelsim/srcs directory.

export_simulation \
      -simulator modelsim \
      -directory proj/test_modelsim \
      -ip_user_files_dir project_1/project_1.ip_user_files_dir \
      -ipstatic_source_dir project_1/project_1.ip_user_files_dir/ipstatic \
      -lib_map_path /design/compiled_libs/modelsim/lib \
      -export_source_files \
      -use_ip_compiled_libs

Generate a simulation script for project project_1/project_1.xpr for the questa simulator. Use the pre-compiled IP static library from the design/compiled_libs/questa/lib directory, set source file paths to the absolute format and run simulator tools in 32bit mode.

export_simulation \
      -simulator questa \
      -directory proj/test_questa \
      -ip_user_files_dir project_1/project_1.ip_user_files_dir \
      -ipstatic_source_dir project_1/project_1.ip_user_files_dir/ipstatic \
      -lib_map_path design/compiled_libs/questa/lib \
      -absolute_path \
      -32bit \
      -use_ip_compiled_libs

Generate a simulation script for the clk_core IP for the xcelium simulator. Use pre-compiled IP static library from the /design/compiled_libs/xcelium/lib directory and overwrite the existing script named test_ip_xcelium.sh in the output directory.

export_simulation \
      -simulator xcelium \
      -of_objects [get_ips clk_core] \
      -directory proj/test_xcelium \
      -ip_user_files_dir project_1/project_1.ip_user_files_dir \
      -ipstatic_source_dir project_1/project_1.ip_user_files_dir/ipstatic \
      -lib_map_path /design/compiled_libs/xcelium/lib \
      -script_name output/test_ip_xcelium.sh \
      -force \
      -use_ip_compiled_libs

Generate and execute a simulation script for the clk_core BD for the vcs simulator. Pass HEX_VAR verilog define, pass INCREMENT vhdl generic, pass more options for vlogan and vcs and run simulation for 4000ns.

  1. Export the script for the clk_core IP.
    export_simulation \ -simulator vcs \ -of_objects [get_files clk_core.bd] \ -directory xp/clk_core/vcs \ -ip_user_files_dir project_1/project_1.ip_user_files_dir \ -ipstatic_source_dir project_1/project_1.ip_user_files_dir/ipstatic \ -lib_map_path /design/compiled_libs/vcs/lib \
    -script_name output/test_ip_vcs.sh \ -define [list {HEX_VAR=4'b0101}] \ -generic [list {INCREMENT=10}] \ -more_options \ [list {vcs.compile.vlogan:-V} {vcs.elaborate.vcs:-timescale 1ps/1ps}] \ -runtime 4000ns \
    -use_ip_compiled_libs
  2. Verify the simulation for the clk_core IP.
    cd xp/char_fifo/vcs ./verify.sh

Generate a simulation script for the current simulation fileset for the riviera simulator. Include verilog header files from the fifo/incl directory and run simulation for 3000ns.

export_simulation \
      -simulator riviera \
      -directory proj/test_riviera \
      -ip_user_files_dir project_1/project_1.ip_user_files_dir \
      -ipstatic_source_dir /project_1/project_1.ip_user_files_dir/ipstatic \
      -lib_map_path /design/compiled_libs/riviera/lib \
      -include [list {fifo/incl}] \
      -runtime 3000ns \
      -use_ip_compiled_libs

Generate a simulation script for all simulators. Use pre-compiled IP static library from the respective simulator directory paths specified with the -lib_map_path switch.

export_simulation \
      -simulator all \
      -directory proj/test_sim \
      -ip_user_files_dir project_1/project_1.ip_user_files_dir \
      -ipstatic_source_dir project_1/project_1.ip_user_files_dir/ipstatic \
      -lib_map_path [list {xsim=/compiled_libs/xsim/lib} \
                          {modelsim=/compiled_libs/modelsim/lib}  \
                          {questa=/compiled_libs/questa/lib}  \
                          {xcelium=/compiled_libs/xcelium/lib}  \
                          {vcs=/compiled_libs/vcs/lib}  \
                          {riviera=/compiled_libs/riviera/lib}  \
                          {activehdl=/compiled_libs/activehdl/lib} ] \
      -use_ip_compiled_libs

See Also