Current Step Load Assumptions

Versal Adaptive SoC PCB Design User Guide (UG863)

Document ID
UG863
Release Date
2024-04-01
Revision
1.8 English

The step load is the percentage of the dynamic current that is expected to be demanded at any given switching event. This is the instantaneous current that is provided primarily by the decoupling capacitors until the regulators can respond. The PDM tool has predefined step load percentages for each rail (with VCCINT being adjustable per the specific nature of the system design). As a point of reference, the current consumption of VCCINT has the most notable effect on the amount of decoupling required by the system, so it is important to ensure the step load percentage is as accurate as possible. The PDM tool defaults to 25% step load for VCCINT, but you can adjust as needed based on your planned application.