Device Resource Utilization

Versal Adaptive SoC PCB Design User Guide (UG863)

Document ID
UG863
Release Date
2023-09-14
Revision
1.7 English

The amount of decoupling required is primarily determined by the amount of power utilized by the design. The power can be accurately estimated by using the PDM tool. By entering such usage parameters as the number of logic cells and DSPs, an accurate current power profile can be obtained.

Resource utilization consists (in part) of:

  • AI Engine: Number of cores used, frequency, loading, and read/write rate
  • Logic: Number of registers and LUTs, toggles rates, and frequency
  • Block RAM: Number of block RAMs, toggles rates, enable rates, and frequencies
  • URAM: Number of UltraRAMs, toggles rates, enable rates, and frequencies
  • DSP: Number of DSP blocks, toggles rates, enable rates, and frequencies
  • GTY: Number of GTY transceivers used, types (PCIe or MRMAC), and frequencies
  • Processing System: Low Power Domain (LP): Processor speeds, loading, and interconnect
  • Processing System: Full Power Domain (FP): Processor speeds, loading, and interconnect
  • Processing System: I/O (MIO): Interfaces types (USB, QSPI, and eMMC) and speeds
  • XPIO: I/O standards, enable rates, and frequencies
  • HDIO: I/O standards, enable rates, and frequencies