GTY/GTYP Transceiver Interfaces

Versal Adaptive SoC PCB Design User Guide (UG863)

Document ID
UG863
Release Date
2023-09-14
Revision
1.7 English

For GTY/GTYP transceiver interfaces such as DisplayPort, SGMII, PCIe® , SATA, and USB3.0, refer to Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002). See below for additional PCIe and CPM guidance.

For CPM4/GTY based designs for PCIe:

  • Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)
  • Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)

For GTY based soft PHY for PCIe, see Versal Adaptive SoC PCIe PHY LogiCORE IP Product Guide (PG345).

For PL PCIE4/GTY based designs for PCIe:

  • Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)
  • Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

PCIe Reset

The PCIe reset pin can be forwarded to a compatible MIO pin. See the Designing with the Subsystem section in Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344).

For HSDP, refer to the HSDP Target Interface section in SmartLynq+ Module User Guide (UG1514) for guidance.