- For interfacing with PHYs with adjustable internal delays, skew between GEMx_TX_DATA[0:3]/GEMx_TX_CTRL and GEMx_TX_CLK should be within 50 ps.
- For interfacing with PHYs with adjustable internal delays, skew between GEMx_RX_DATA[0:3]/GEMx_RX_CTRL and GEMx_RX_CLK should be within 50 ps.
- When interfacing with a PHY without internal delays, the TX_DATA[0:3] lines should be skewed on the board with respect to TX_CLK to meet the setup/hold requirements of the PHY. The RX_DATA[0:3] should be skewed on the board with respect to RX_CLK to meet the setup/hold requirements of the Versal device.
- Ensure setup and hold times are met for the Versal and Ethernet PHY devices.
- To verify setup and hold times are met, refer to the formulas below:
- Definitions:
- Clock_Period = The clock period of the Ethernet interface clock GEMx_TX_CLK or GEMx_RX_CLK (1/FGEMTXCLK or 1/FGEMRXCLK)
- TGEMTXCKO max/min = Versal adaptive SoC TX clock to output delay
- TGEMRXDCK = Versal adaptive SoC RX setup time
- TGEMRXCKD = Versal adaptive SoC RX hold time
- CTO max/min (Ethernet) = Ethernet device clock to output delay (See Ethernet device datasheet)
- Tsetup (Ethernet) = Ethernet device setup time (see Ethernet device datasheet)
- Thold (Ethernet) = Ethernet device hold time (See Ethernet device datasheet)
- Max_PCB_trace_delay = The maximum PCB trace delay among GEMx_TX_CLK, GEMx_TX_DATA[0:3] (TX), and GEMx_RX_CLK, GEMx_RX_DATA[0:3] (RX)
- Min_PCB_trace_delay = The minimum PCB trace delay among GEMx_TX_CLK, GEMx_TX_DATA[0:3] (TX), and GEMx_RX_CLK, GEMx_RX_DATA[0:3] (RX)
- Formulas:
- TX:
- Tsetup (Ethernet) ≤ TGEMTXCKO max + (skew between GEMx_TX_CLK PCB trace delay and maximum GEMx_TX_DATA[0:3] PCB trace delay)
- Thold (Ethernet) ≤ TGEMTXCKO min + (skew between
GEMx_TX_CLK PCB trace delay and minimum
GEMx_TX_DATA[0:3] PCB trace delay)Note: See the first two bullets in this section regarding skew guidelines.
- RX:
- TGEMRXDCK ≤ CTO max (Ethernet) + (skew between GEMx_RX_CLK PCB trace delay and maximum GEMx_RX_DATA[0:3] PCB trace delay)
- TGEMRXCKD ≤
CTO min (Ethernet) + (skew between GEMx_RX_CLK PCB trace
delay and minimum GEMx_RX_DATA[0:3] PCB trace
delay)Note: See the first two bullets in this section regarding skew guidelines.
- TX:
- Definitions:
- Ensure proper signal integrity on the PCB:
- No reflections at the near or far end of the Versal device:
- 30Ω series terminations can be placed on the GEMx_TX_CLK line near the
adaptive SoC and the GEMx_RX_CLK line near the PHY, as close to
the respective pins as possible.
- This is optimal for most setups
- Ensure good signal integrity via simulation
- 30Ω series terminations can be placed on the GEMx_TX_CLK line near the
adaptive SoC and the GEMx_RX_CLK line near the PHY, as close to
the respective pins as possible.
- Ensure VIH/VIL and
VOH/VOL
levels are met for both the Versal
and Ethernet devices
- Values can be found in the PSIO Levels section of the Versal adaptive SoC data sheets.
- Be sure to choose the correct levels for the voltage used (i.e., LVCMOS18, LVCMOS33).
- No reflections at the near or far end of the Versal device:
- When interfacing with a PHY with adjustable TX/RX delays, the PHY internal delays might be adjusted by software to meet the setup/hold requirements of the Versal and PHY devices.