I/O Bank and GT Quad Number Differences

Versal Adaptive SoC PCB Design User Guide (UG863)

Document ID
UG863
Release Date
2024-04-01
Revision
1.8 English

Certain Versal devices that are footprint compatible in a package might have different I/O bank and transceiver Quad numbers associated with the same package pins. Depending on where these banks are physically located on the die, certain multi-bank interfaces (such as memory or transceiver) could be impacted with regard to migration from one device to another.

Refer to the I/O Bank Migration and Transceiver Quad Migration tables in Versal Adaptive SoC Packaging and Pinouts Architecture Manual (AM013) for the bank and transceiver Quad numbering differences. To determine bank locations on a die, refer to the Die Level Bank Numbering Overview section of Versal Adaptive SoC Packaging and Pinouts Architecture Manual (AM013).

The example below shows a successful migration path despite bank number changes between the two different devices.

Example: Planning Ahead for Bank Number Changes

As shown in the following figure, banks 803, 804, and 805 in the XCVM1402_VFVD1760 connect to the same pins as banks 706, 707, and 708 in the XCVM1802_VFVD1760 because they share the same alphabetic code (G, H, I) indicating the same pin location. All three banks remain part of the same triplet on each respective die. This would result in a successful migration for interfaces that utilize these three banks, with pin flight times being the only potential difference.

Figure 1. Snippet of I/O Migration Table