I2C

Versal Adaptive SoC PCB Design User Guide (UG863)

Document ID
UG863
Release Date
2024-04-01
Revision
1.8 English
  • Place 4.7 kΩ pull-up resistors at the far end of the serial clock lines (LPD_I2Cx_SCL) and serial data lines (LPD_I2Cx_SDA) furthest from the Versal adaptive SoC.
  • A level-shifter/repeater might be required depending on the particular multiplexers used.
  • Ensure VIH/VIL and VOH/VOL levels are met for both the Versal and I2C devices
    • Versal device values can be found in the PSIO Levels section of the Versal adaptive SoC data sheets.
    • Be sure to choose the correct levels for the voltage used (that is, LVCMOS18, LVCMOS33).