Octal SPI

Versal Adaptive SoC PCB Design User Guide (UG863)
Document ID
UG863
Release Date
2024-04-01
Revision
1.8 English
  • Place 4.7–10 kΩ pull-up resistors to VCCO_500 on the OSPIx_CS_b and OSPI_RST_b lines.
  • Skew between OSPI_IO[7:0]/OSPI_DS and OSPI_CLK should be within 50 ps.
  • It is highly recommended to perform a signal integrity analysis on the clock line at the near end (close to the Versal adaptive SoC) and far end.
  • Ensure proper signal integrity on the PCB
    • No reflections on the PCB at far or near ends of the Versal device.
  • Ensure VIH/VIL and VOH/VOL levels are met for the Versal and flash devices.
    • Values can be found in the PSIO Levels section of the Versal adaptive SoC data sheets.
    • Be sure to choose the correct levels for the voltage used (i.e., LVCMOS18, LVCMOS33).
  • For reads, ensure that the drive strength matches the load being driven for optimal read performance:
    • This especially applies if adding any series resistance on the OSPI_CLK and/or OSPI_IO[7:0] lines.
  • For all frequencies, ensure setup and hold times are met for both the Versal adaptive SoC and OSPI device.
  • Refer to the following formulas to ensure setup/hold times are met, and to determine maximum frequency of operation:
    • Definitions:
      • Clock_Period = The clock period of the OSPI interface clock OSPI_CLK (1/FOSPI_CLK)
      • TOSPICKO = Versal adaptive SoC OSPI clock to output delay
      • TOSPIDCK = Versal adaptive SoC OSPI setup time
      • TOSPICKD = Versal adaptive SoC OSPI hold time
      • Tsetup (flash) = OSPI device setup time (see OSPI device datasheet)
      • Thold (flash) = OSPI device hold time (See OSPI device datasheet)
      • CTO max/min (flash) = Flash device clock to output delay (See OSPI device datasheet)
      • Max_PCB_trace_delay = The maximum PCB trace delay among OSPI_CLK, OSPI_IO[7:0]
      • Min_PCB_trace_delay = The minimum PCB trace delay among OSPI_CLK, OSPI_IO[7:0]
    • Formulas:
      • Write (PHY and Non-PHY Mode)
        • SDR Mode: Tsetup (flash) ≤ Clock_Period – TOSPICKO(max) – (skew between OSPI_CLK PCB trace delay and maximum OSPI_IO[7:0] PCB trace delay)
        • DDR Mode: Tsetup (flash) ≤ Clock_Period/2 – TOSPICKO(max) – (skew between CLK PCB trace delay and maximum OSPI_IO[7:0] PCB trace delay)
        • Thold (flash) ≤ TOSPICKO(min) – (skew between CLK PCB trace delay and minimum OSPI_IO[7:0] PCB trace delay)
          Note: See second bullet in this section regarding skew guidelines.
      • Read (Non-PHY Mode (< 50 MHz))
        • TOSPIDCK ≤ Clock_Period – CTO max (flash) + 2 x Max_PCB_trace_delay(OSPI_IO[7:0])
        • TOSPICKD ≤ CTO min (flash) + 2 x Min_PCB_trace_delay(OSPI_IO[7:0])
          Note: See second bullet in this section regarding skew guidelines.
  • For frequencies greater than 50 MHz (PHY Mode), for read, due to RX tuning, the maximum frequency is not a function of the PCB trace delay. Simulations can be performed for RX tuning and to ensure setup/hold times of the Versal and flash devices are met.
CAUTION:
To boot the Versal adaptive SoC in OSPI boot mode, the octal SPI flash must be compatible and support the SDR commands listed in the Octal SPI Boot Mode section in Versal Adaptive SoC Technical Reference Manual (AM011).