This section provides PCB design guidelines for DDR4 interfaces. Connections
between the adaptive SoC and DDR4 device(s) are defined along with physical design rules
and timing constraints. Both component and DIMM architectures are covered.
Important: All routing
guidelines in this section must be followed to achieve the maximum data rates
specified in the Versal
adaptive SoC data sheets. Customers could have unique or specific designs
with particular violations of some rules. In these scenarios, design or routing
trade-offs have to be taken in other routing parameters to mitigate the risk.
System-level channel signal integrity simulations are required to evaluate such
trade-offs. It is important to read Required Memory Routing Guidelines for All Interfaces before continuing with this section.