PMC Dedicated Pins

Versal Adaptive SoC PCB Design User Guide (UG863)

Document ID
UG863
Release Date
2023-09-14
Revision
1.7 English

Versal adaptive SoC dedicated pins assist with system management. The dedicated pins provide key functions such as boot mode selection, external reference clock input, power-on reset input, JTAG interface, status signals, error signals, and crystal oscillator pins for the real-time clock (RTC).

  • Connect DONE to a 4.7 kΩ pull-up resistor to VCCO_503 near the Versal adaptive SoC.
    • Consider connecting DONE to an LED driver that lights an LED as a visual confirmation of a successful boot when DONE is High.
  • Connect ERROR_OUT to a 4.7 kΩ pull-up resistor to VCCO_503 near the Versal adaptive SoC.
    • Consider connecting ERROR_OUT to an LED driver that lights an LED as a visual indicator of an error when ERROR_OUT is High.
  • Connect POR_B to a 4.7 kΩ pull-up resistor to VCCO_503 near the Versal adaptive SoC
    • For devices with multiple POR_B pins, connect all pins together at the PCB level. Only one pull-up resistor is needed regardless of the number of POR_B pins.
    • See the Power Design sheet in the Power Design Manager (PDM) tool (download at www.xilinx.com/power) for additional POR_B requirements during power-on and power-down.
  • For devices with multiple PUDC_B pins, connect all pins together at the PCB level.
    • PUDC_B should be connected and not left floating
      • Connect High for programmable logic I/Os to be put in tristate during configuration (1.0 kΩ to VCCO_503).
      • Connect Low to active internal pull-ups at each programmable logic I/O during configuration
  • For device with multiple VCC_BATT pins, connect all pins together at the PCB level
  • For devices with multiple VCC_FUSE pins, connect all pins together at the PCB level
  • Connect TMS, TCK, TDI, and TDO to a JTAG connector for a JTAG cable/controller according to JTAG standards for JTAG board tests and Versal device debug. See the Platform Cable USB II Data Sheet (DS593) for example JTAG cable connections.
  • Place 4.7 kΩ pull-up resistors on the TMS, TCK, and TDI lines to VCCO_503 near the Versal adaptive SoC.
    • All interconnected JTAG chains should be powered by the same voltage rail. Or, if different rails are used, they should all be powered at the same time.
    • TCK is a critical signal. Ensure signal integrity is good at the TCK pin.
  • See the Primary Boot Modes table in the Versal Adaptive SoC Technical Reference Manual (AM011) for your desired primary boot mode setting and for the JTAG boot mode setting. Connect the MODE[3:0] pins to VCCO_503 via a 4.7 kΩ (or stronger) resistor or to ground via a 1 kΩ (or stronger) resistor to achieve the desired primary boot mode setting. Add switches or jumpers to allow the MODE[3:0] pins to be set to the alternate JTAG boot mode for board manufacturing JTAG tests, board bring-up, or device debug.
    • For devices with multiple MODE[3:0] pins, connect all respective pins together at the PCB level (MODE0 to MODE0, MODE1 to MODE1, MODE2 to MODE2, MODE3 to MODE3). Only one pull-up or pull-down resistor is needed on each MODE pin regardless of the number of pins.
  • Select SSI technology devices that have multiple MODE[3:0], POR_B, and PUDC_B pin sets for each SLR with power rails that control all of these signals tied together.
  • Connect REF_CLK to a clock generator providing a 27–60 MHz clock (typically 33 MHz). The clock must be a single-ended LVCMOS signal using the same voltage level as VCCO_503. Signal integrity analysis should be run to determine the need for clock buffering and/or termination. Termination can be either a series termination at the clock source or a Thevenin termination as close as possible to the REF_CLK pin of the adaptive SoC. See Versal adaptive SoC data sheets for timing information for REF_CLK.

    Important: Versal devices (e.g., XCVP1802) based on stacked silicon interconnect (SSI) technology that contain greater than two super-logic regions (SLRs) typically have multiple reference clock pins (e.g., REF_CLK[1:0]). For device package pinouts with multiple reference clock pins, use one on-board clock source connected to a 1:N buffer so that each REF_CLK pin receives its own copy of the clock source from the 1:N buffer. See the SLR Count and Dimensions table in the Versal Architecture and Product Data Sheet: Overview (DS950).
  • If using the real-time clock (RTC), connect a battery between the VCC_BATT pin and GND, and connect a crystal circuit as shown in the example below to the RTC PADs. See the Versal adaptive SoC data sheets for the RTC crystal and VCC_BATT requirements.
    • Keep PADI trace to one inch or shorter to minimize added capacitance. If the real-time clock is not being used, connect PADI to ground.
    • Keep PADO trace to one inch or shorter to minimize added capacitance. If the real-time clock is not being used, leave PADO floating.
Figure 1. Crystal Circuit Example