Planar Resistance Recommendations

Versal Adaptive SoC PCB Design User Guide (UG863)

Document ID
UG863
Release Date
2024-04-01
Revision
1.8 English

It is important to design the physical power planes in order to transfer the power required on the rail with minimal IR voltage loss. Narrow planes, or planes with many via keep-out circles, can lead to excessive IR drop that can be difficult to overcome by regulators, even with proper sense line placement. AMD highly recommends that a proper power analysis be done to ensure that all DC and AC specifications are followed, including simulations before and after PCB layout.

For a starting point for plane design with regard to IR drop, each power plane should be targeted to have a voltage drop of no greater than the recommended voltage delta (typical – minimum) when subjected to the total current expected on the rail. This voltage drop, divided by the total current, provides the maximum amount of resistance for the rail.

RMAX = (Recommended Typical Voltage – Recommended Minimum Voltage)/Total Current

The recommended typical and minimum voltage values can be found in the datasheet, and the total current can be found in the PDM tool.

This maximum resistance value is solely with regard to the IR drop across the plane and does not take into account any thermal or other requirements. The actual maximum plane resistance might be lower when all other factors are considered.

Example 1: Planar Resistance for VCCINT

Assuming a mid-voltage device (M), the typical voltage for VCCINT is 0.80V. The corresponding minimum voltage is 0.775V. The voltage drop is 0.80V – 0.775V = 0.025, or 25 mV. Assuming a design that has 99A total current on VCCINT, RVCCINT = 0.025V/99A = 0.252 mΩ.

Example 2: Planar Resistance for VCCAUX

According to the datasheet, the typical VCCAUX value is 1.50V, and the minimum value is 1.455V. The voltage drop is 1.50V – 1.455V = 0.045V, or 45 mV. Assuming a design with 8A total current, the maximum resistance is 0.045V/8A = 5.625 mΩ.