Power Distribution System in Versal ACAPs

Versal ACAP PCB Design User Guide (UG863)

Document ID: UG863
Release Date: 2022-12-14
Revision: 1.6 English

Overview
Introduction to Versal ACAP
Navigating Content by Design Process
PCB Design Features
Differences from Previous Generations
Power Distribution System in Versal ACAPs
Introduction
Versal ACAP Power Rails
Unused VCCO Banks
Power Management Scenarios
Recommended Decoupling Capacitor Quantities for Versal Devices
Decoupling Capacitor Methodology
Device Resource Utilization
Current Step Load Assumptions
Voltage Ripple Assumptions
Target Impedance
Planar Resistance Recommendations
PCB Routing for Remote Voltage Sense Lines
Purpose of Sense Lines
Limitations of Sense Lines
ACAPs with Dedicated Sense Pins
ACAPs without Dedicated Sense Pins
The Use of Routing Tunnels and Sense Lines
PCB Guidelines for Memory Interfaces
Required Memory Routing Guidelines for All Interfaces
Reference Material Specifications
Adjusting for Different Stack-Ups
PCB Routing Guidelines for DDR4 Interfaces
Signals and Connections for DDR4 Interfaces
Clamshell Topology
Utilizing Address Mirroring to Ease Clamshell Routing
Physical Design Rules for DDR4 Signals
Routing Rule Changes for Thicker Printed Circuit Boards
Timing Constraint Rules for DDR4 Signals
PCB Routing Guidelines for LPDDR4/4x Interfaces
Signals and Connections for LPDDR4/4x Interfaces
Physical Design Rules for LPDDR4/4x Signals
Timing Constraint Rules for LPDDR4/4x Signals
PCB Routing Guidelines for RLDRAM3 Interfaces
Signals and Connections for RLDRAM3 Interfaces
Physical Design Rules for RLDRAM3 Signals
Timing Constraint Rules for RLDRAM3 Signals
PCB Routing Guidelines for QDR-IV Interfaces
Signals and Connections for QDR-IV Applications
Physical Design Rules for QDR-IV Signals
Timing Constraint Rules for QDR-IV Signals
PCB Guidelines for PS, PMC, MIPI, and GTY/GTYP Transceiver Interfaces
GTY/GTYP Transceiver Interfaces
PMC Dedicated Pins
CAN FD
Gigabit Ethernet MAC 10/100/1000 RGMII
I3C and I2C
MIPI
Octal SPI
Quad SPI
SD/SDIO/eMMC
SelectMAP
SPI
Trace Port Interface Unit
Triple Time Counter
UART
USB 2.0
System Windowed Watchdog Timer
Migration between Versal Devices and Packages
Versal ACAP Migration Checklist
Footprint Compatibility between Packages
Differences in XPIO, HDIO, and Transceiver Count
Package Dimensions
VCCSDFEC Rail
Differences in Transceiver Counts
Differences in XPIO Performance
XPIO Bank Fabric Access Limitations
GTYP Transceiver Fabric Access Limitations
I/O Bank and GT Quad Number Differences
GT_RCAL and GT_RREF Differences
Decoupling Capacitors Guidelines
Package Flight Time Differences
Reserved Sense Lines
IO_VR_700, IO_VR_800 Pin Differences
Material Properties and Insertion Losses
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Revision History
Please Read: Important Legal Notices

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