Power Management Scenarios

Versal Adaptive SoC PCB Design User Guide (UG863)

Document ID
UG863
Release Date
2024-04-01
Revision
1.8 English

While it is possible to power each rail with its own voltage regulator module (VRM), it can be beneficial both cost-wise and area-wise to consolidate power rails that share the same voltage. AMD has defined two power management scenarios that can be used depending on design needs. These power management scenarios are further defined into sub-categories depending on the core voltage and whether or not the processing system (PS) is powered at a higher voltage.

Minimum Rails
This category aims to reduce the amount of regulators and unique power rails on the board. This saves on complexity, component count, and board space at the expense of reduced flexibility in regards to powering individual rails.
Full Power Management
This category allows for the greatest flexibility in regards to powering individual rails, resulting in power savings, though with increased complexity, component count, and board space.

The Power Design Manager (PDM) tool (download at www.xilinx.com/power) contains the full scenario descriptions with rail sequencing requirements, rail groupings, voltage values, voltage tolerances, and graphical images for all of the scenarios. The PDM tool is intended be used along with user power estimation to ensure the most robust power system design.

Note: Power delivery reference designs using these supported rail consolidations are available from Power Efficiency.