Reserved Sense Lines

Versal Adaptive SoC PCB Design User Guide (UG863)

Document ID
UG863
Release Date
2024-04-01
Revision
1.8 English

Some Versal devices have reserved sense pins that are not connected to the die and should be left floating. These pins are in the form of RSVD_VCCINT_SENSE and RSVD_GND_SENSE. These pins are shown to indicate that they might be present in other devices in the same package and can be used for migration purposes.