SD/SDIO/eMMC

Versal Adaptive SoC PCB Design User Guide (UG863)
Document ID
UG863
Release Date
2024-04-01
Revision
1.8 English

eMMC

  • Pull-up resistors are required on EMMCx_DATA[7:0] and EMMCx_CMD per JEDEC specification JESD84-B451, Embedded Multi-media Card (eMMC)
  • Skew between EMMCx_DATA[7:0]/EMMCx_CMD and EMMCx_CLK should be within 50 ps.
    • For optimum performance, limit trace delays to ~1 ns between the adaptive SoC and eMMC device
  • For all frequencies, ensure setup and hold times are met for the Versal and eMMC device. To verify setup and hold times are met, and to determine maximum operating frequency, refer to the formulas below:
    • Definitions:
      • Clock_Period = The clock period of the eMMC interface clock EMMCx_CLK (1/FEMMCSCLK)
      • TEMMCCKO max/min = Versal adaptive SoC eMMC clock to output delay
      • TEMMCDCK = Versal adaptive SoC eMMC setup time
      • TEMMCCKD = Versal adaptive SoC eMMC hold time
      • CTO max/min (flash) = Flash device clock to output delay (see eMMC device datasheet)
      • Tsetup (flash) = eMMC device setup time (see eMMC device datasheet)
      • Thold (flash) = eMMC device hold time (see eMMC device datasheet)
      • Max_PCB_trace_delay = The maximum PCB trace delay among EMMCx_CLK, EMMCx_DATA[7:0]
      • Min_PCB_trace_delay = The minimum PCB trace delay among EMMCx_CLK, EMMCx_DATA[7:0]
    • Formulas:
      • Write:
        • eMMC Standard, DDR Modes: Tsetup (flash) ≤ Clock_Period/2 – TEMMCCKO max – (skew between EMMCx_CLK PCB trace delay and maximum EMMCx_DATA[7:0] PCB trace delay)
        • All other Modes: Tsetup (flash) ≤ Clock_Period – TEMMCCKO max – (skew between EMMCx_CLK PCB trace delay and maximum EMMCx_DATA[7:0] PCB trace delay)
        • Thold (flash) ≤ TEMMCCKO min – (skew between EMMCx_CLK PCB trace delay and minimum EMMCx_DATA[7:0] PCB trace delay)
          Note: See third bullet in this section regarding skew guidelines.
      • Read (Non-DLL Mode):
        • eMMC Standard Mode: Tsetup (Versal adaptive SoC) ≤ Clock_Period/2 – CTO max (flash) + 2 x Max_PCB_trace_delay
        • Thold(Versal adaptive SoC) < CTO min (flash) + 2 x Min_PCB_trace_delay
          Note: The 2X PCB trace delay in both equations is for round-trip time to/from the flash device.
      • For frequencies greater than 25 MHz (DLL Mode), due to RX timing, the maximum frequency is not a function of the PCB trace delay. RX tuning simulations can be performed to ensure setup/hold times are met for the Versal and flash devices.
  • Ensure proper signal integrity on the PCB:
    • No reflections at near or far end of Versal device
      • 30Ω series terminations can be placed on the EMMCx_CLK, EMMCx_CMD, and EMMC_DATA[7:0] lines, as close to the adaptive SoC pins as possible.
        • This is optimal for most setups
        • Ensure good signal integrity via simulation
    • Ensure VIH/VIL and VOH/VOL levels are met for both the Versal and flash devices.
    • Values can be found in the PSIO Levels section of the Versal adaptive SoC data sheets.
      • Be sure to choose the correct levels for the voltage used (that is, LVCMOS18, LVCMOS33).

SD/SDIO

  • A level shifter might be required depending on the particular voltages (such as for SD 3.0) used on the Versal adaptive SoC and SD chip.
  • Asynchronous signals SDx_DETECT and SDx_WP have no timing relationship to SDx_CLK.
  • The SDx_DETECT and SDx_WP lines should both be pulled up with their own 4.7 kΩ resistors to the MIO voltage. When using microSD, SDx_WP and SDx_DETECT can be no connects.
  • A 10 kΩ pull-up resistor should be added to SDx_DATA[3] on the SD card side of the level shifter with direction pins.
  • When using an auto-direction level shifter, 15kΩ pull-up resistors should be added to the SDx_DATA[1], SDx_DATA[2], and SDx_DATA[3] lines near the level shifter.
  • When using an auto-direction level shifter, SDx_DIR_CMD, SDx_DIR0, and SDx_DIR1 can be no-connects.
  • Skew between SDx_DATA[3:0]/SDx_CMD and SDx_CLK should be within ±50 ps.
  • For optimum performance, limit trace delays to 1.0 ns between the adaptive SoC and SD card.
  • For all frequencies, ensure setup and hold times are met for the Versal and SD devices. To verify setup and hold times are met, and to determine maximum operating frequency, refer to the formulas below:
    • Definitions:
      • Clock_Period = The clock period of the SD interface clock SDx_CLK
      • TSDCKO max/min = Versal adaptive SoC SD clock to output delay
      • TSDDCK = Versal adaptive SoC SD setup time
      • TSDCKD = Versal adaptive SoC SD hold time
      • CTO_max/min (flash) = Flash device clock to output delay (see SD device datasheet)
      • Tsetup (flash) = SD device setup time (see SD device datasheet)
      • Thold (flash) = SD device hold time (See SD device datasheet)
      • Max_PCB_trace_delay = The maximum PCB trace delay among SDx_CLK, SDx_DATA[3:0]
      • Min_PCB_trace_delay = The minimum PCB trace delay among SDx_CLK, SDx_DATA[3:0]
      • SD_Level_Shifter_CLK_Propagation_delay_min/max = The delay of the clock line through the level shifter
        • There can be different values depending on the direction of the signal (that is, "Host-to-Card" and "Card-to-Host")
      • SD_Level_Shifter_DATA_Propagation_delay_min/max = The delay of the shortest/longest data line through the level shifter
        • There can be different values depending on the direction of the signal (that is, "Host-to-Card" and "Card-to-Host")
      • SD_Level_Shifter_Propagation_delay_min/max = The minimum/maximum level shifter propagation delay between SDx_CLK, SDx_DATA[3:0]
        • There can be different values depending on the direction of the signal (that is, "Host-to-Card" and "Card-to-Host")
    • Formulas:
      • Write:
        • SD Default, DDR Modes: Tsetup (flash) ≤ Clock_Period/2 – TSDCKO max – (skew between SDx_CLK PCB trace delay and maximum SDx_DATA[3:0] PCB trace delay) – SD_Level_Shifter_Propagation_delay_max
        • All other Modes: Tsetup (flash) ≤ Clock_Period – TSDCKO max – (skew between SDx_CLK PCB trace delay and maximum SDx_DATA[3:0] PCB trace delay) – SD_Level_Shifter_Propagation_delay_max
        • Thold (flash) ≤ TSDCKO min – (skew between SDx_CLK PCB trace delay and minimum SDx_DATA[3:0] PCB trace delay) – SD_Level_Shifter_Propagation_delay_min
          Note: See seventh bullet in this section regarding skew guidelines.
      • Read (Non-DLL Mode):
        • SD Default Mode: TSDDCK ≤ Clock_Period/2 – CTOmax (flash) – 2 x Max_PCB_trace_delay – (maximum level shifter delay(card to host)) – SD_Level_Shifter_Propagation_delay_max(host-to-card)
        • SDR12: TSDDCK ≤ Clock_Period – CTOmax (flash) + 2 x Max_PCB_trace_delay – (maximum level shifter delay(card to host)) – SD_Level_Shifter_Propagation_delay_max (host-to-card)
        • TSDCKD ≤ CTOmin (flash) + 2*Min_PCB_trace_delay + SD_Level_Shifter_Propagation_delay_min(card-to-host) + SD_Level_Shifter_Propagation_delay_min(host-to-card)
          Note: The 2X PCB trace delay in both equations is for round-trip time to/from the flash device.
      • For frequencies greater than 25 MHz (DLL Mode), due to RX timing, the maximum frequency is not a function of the PCB trace delay. RX tuning simulations can be performed to ensure setup/hold times are met for the Versal and flash devices.
  • Ensure proper signal integrity on the PCB
    • No reflections at near or far end of Versal device
      • 30Ω series terminations can be placed on the SDx_CLK, SDx_CMD, and SDx_DATA[3:0] lines, as close to the adaptive SoC pins as possible.
        • This is optimal for most setups
        • Ensure good signal integrity via simulation
    • Ensure VIH/VIL and VOH/VOL levels are met for both the Versal and flash devices
      • Values can be found in the PSIO Levels section of the Versal adaptive SoC data sheets.
        • Be sure to choose the correct levels for the voltage used (that is, LVCMOS18, LVCMOS33).