Some Versal adaptive SoCs have a dedicated “tunnel” of BGA pins that are specifically placed so as to provide for the maximum amount of power delivery with minimal IR drop. This so-called routing tunnel removes via keep-out areas that result in holes in the power plane. The pins in the routing tunnel do not connect directly to the die on the adaptive SoC. These pins are only present so that the PCB routing planes for VCCINT do not require via keep-out holes from other signals or power rails.
The following figure shows the BGA pin field of the VC1902-A2197 device with the VCCINT pin field outlined. The pins in the routing tunnel area do not require via keep-outs to the VCCINT planes below, so there are no holes in the metal planes that supply power to VCCINT. Optimal sense line placement is at any point on the VCCINT pin field that is outside of the routing tunnel.
The following figure shows the BGA pin field of the VM1802-C1760 device with the VCCINT pin field outlined. There is no routing tunnel on this device, so the power planes on the BGA have via keep-outs that reduce power delivery efficiency. Sense line placements would be recommended anywhere near the center of this pin field.
