When operating the trace port interface unit (TPIU) in MIO mode, the trace clock output should be delayed by approximately one half clock period. This can be done on the PCB, or by the debugging device (ARM_DSTREAM, Lauterbach, or Agilent).
Ensure VIH/VIL and VOH/VOL levels are met for both the Versal and TPIU devices
- Versal device values can be found in the PSIO Levels section of the Versal adaptive SoC data sheets.
- Be sure to choose the correct levels for the voltage used (i.e., LVCMOS18, LVCMOS33).