UART

Versal Adaptive SoC PCB Design User Guide (UG863)

Document ID
UG863
Release Date
2024-04-01
Revision
1.8 English

AMD suggests keeping trace delays below 1.30 ns.

Ensure VIH/VIL and VOH/VOL levels are met for both the Versal and UART devices:

  • Versal device values can be found in the PSIO Levels section of the Versal adaptive SoC data sheets.
  • Be sure to choose the correct levels for the voltage used (i.e., LVCMOS18, LVCMOS33).