USB 2.0

Versal ACAP PCB Design User Guide (UG863)

Document ID
UG863
Release Date
2022-12-14
Revision
1.6 English

ULPI Interface (60 MHz):

  • Skew between USB_ULPI_DATA[7:0]/USP_ULPI_DIR/USB_ULPI_NXT/USB_ULPI_STP and USB_ULPI_CLK should be within 50 ps.
  • For optimum performance, limit trace delays to 1.3 ns between the ACAP and ULPI PHY device
  • Ensure setup and hold times are met for the Versal and ULPI devices. To verify setup and hold times are met, refer to the following formulas:
    • Definitions:
      • Clock_Period = The clock period of the ULPI interface clock USB_ULPI_CLK (1/FULPICLK)
      • TULPICKO = Versal ACAP ULPI Clock to Output Delay
      • TULPIDCK = Versal ACAP ULPI setup time
      • TULPICKD = Versal ACAP ULPI hold time
      • Tsetup (ULPI) = ULPI device setup time (see ULPI device datasheet)
      • Thold (ULPI) = ULPI device hold time (See ULPI device datasheet)
      • CTO max/min (ULPI) = ULPI device clock to output delay (See ULPI device datasheet)
      • Max_PCB_trace_delay = The maximum PCB trace delay among USB_ULPI_CLK, USB_ULPI_DATA[7:0]
      • Min_PCB_trace_delay = The minimum PCB trace delay among USB_ULPI_CLK, USB_ULPI_DATA[7:0]
    • Formulas:
      • ULPI PHY Write
        • Tsetup (ULPI) ≤ Clock_Period – TULPICKO max – 2 x Max_PCB_trace_delay
        • Thold (ULPI) ≤ TULPICKO min + 2 x Min_PCB_trace_delay
      • ULPI PHY Read
        • TULPIDCK ≤ Clock_Period – CTO max (ULPI) – (skew between USB_ULPI_CLK PCB trace delay and maximum USB_ULPI_DATA[7:0] PCB trace delay)
        • TULPICKD ≤ CTO min (ULPI) – (skew between USB_ULPI_CLK PCB trace delay and minimum USB_ULPI_DATA[7:0] PCB trace delay)
  • Ensure proper signal integrity on the PCB:
    • No reflections at near or far end of Versal device.
      • 30Ω series terminations can be placed on the USB_ULPI_DATA[7:0] and USB_ULPI_STP lines, as close to the ACAP pins as possible.
        • This is optimal for most setups.
        • Ensure good signal integrity via simulation.
    • Ensure VIH/VIL and VOH/VOL levels are met for both the Versal and ULPI devices.
      • Values can be found in the PSIO Levels section of the Versal ACAP data sheets.
      • Be sure to choose the correct levels for the voltage used (i.e., LVCMOS18, LVCMOS33).