Utilizing Address Mirroring to Ease Clamshell Routing

Versal Adaptive SoC PCB Design User Guide (UG863)

Document ID
Release Date
1.7 English

While the clamshell topology has advantages such as reduced board space, the asymmetrical nature of the memory device package pin locations can lead to higher routing congestion in the areas under the memory devices between the top and bottom layers. This routing congestion could potentially lead to higher crosstalk due to the inability to include as many ground-return vias as in other topologies, as well as longer stub traces on the top and bottom layers. Address mirroring can be used to change the function of certain pins on a memory device to correspond to the pin directly above or below it. One via can be used for the signal, along with a short stub to the landing pad for each device. Address mirroring is defined in JEDEC specification JESD21-C. Twelve command/address/control pins can be mirrored for DDR4 SDRAM, according to the following table.

Important: It is required that CS0 and Byte 0 (DQ[7:0]) be associated with the non-mirrored devices in order for calibration to complete successfully.
Table 1. Allowable Mirror Pins for DDR4 SDRAM
Memory Controller Pin DRAM Pin (Non-Mirrored) DRAM Pin (Mirrored)
A3 A3 A4
A4 A4 A3
A5 A5 A6
A6 A6 A5
A7 A7 A8
A8 A8 A7
A11 A11 A13
A13 A13 A11
BG0 1 BG0 BG1
BG1 1 BG1 BG0
  1. BG0 and BG1 can only be mirrored when pin BG1 is present on the memory device.