AC voltage ripple (voltage deviation due to transient current events) along with VRM DC tolerance on each rail is assumed to fall within the specifications as defined in the Versal adaptive SoC data sheets. For purposes of determining PCB decoupling, the core rails (VCCINT, VCC_RAM, VCC_SOC, VCC_IO, VCC_PSFP, VCC_PSLP, and VCC_PMC) use a fixed 17 mV for AC ripple in addition to a DC VRM tolerance of 1%. For example, if the Versal adaptive SoC data sheets list a minimum/maximum operating voltage, decoupling capacitors are designed to ensure that the AC ripple stays within 17 mV while the rest of the margin is allocated to account for the 1% DC tolerance of most voltage regulator modules (VRMs).