- After Vivado opens, select Create Project on the Getting Started page.
- Click Next in the New Project wizard.
- Specify the Project Name and Location:
- Project name
-
project_bft
- Project Location
-
<Extract_Dir>/Vivado_Tutorial/Tutorial_Created_Data
- Click Next.
- Select RTL Project as the Project Type and click Next.
- Click the
button and select Add Files.
- Browse to <Extract_Dir>/Vivado_Tutorial/Sources/hdl/
- Press and hold the Ctrl key, and click to select the following files: async_fifo.v, bft.vhdl, FifoBuffer.v, and bft_tb.v.
- Click OK to close the File Browser.
- Click the
button and select Add Directories.
- Select the <Extract_Dir>/Vivado_Tutorial/Sources/hdl/bftLib directory.
- Click Select.
- Click the HDL Sources For column for
the bft_tb.v file and change Synthesis and
Simulation to Simulation only, as shown
in the following figure.
- Click in the Library column for the bftLib, and manually edit the value to change it from xil_defaultlib (or work) to bftLib, as shown in the following figure.
- Enable the check boxes for Copy sources into project, and Add sources from subdirectories.
- Set the Target Language to Verilog to define the language of the netlist generated by Vivado synthesis.
- Set the Simulator Language to Verilog to define the language required by the logic simulator.
- Click Next.
- On the Add Constraints Page, click Add Files.
- Browse to and select <Extract_Dir>/Vivado_Tutorial/Sources/bft_full_kintex7.xdc.
- Click OK to close the File Browser.
- Enable the check box for Copy constraints files
into project.
- Click Next to move to the Default Part page.
- On the Default Part page, click the Family filter and select the Kintex-7 family.
- Scroll to the top of the list and select the xc7k70tfbg484-2 part, and click Next.
- Click Finish to close the New Project
Summary page, and create the project.
The Vivado IDE opens project_bft in the default layout.