Design Flows - 2023.2 English

Vivado Design Suite User Guide: Design Flows Overview (UG892)

Document ID
UG892
Release Date
2023-10-18
Version
2023.2 English

The following figure shows the high-level design flow in the Vivado Design Suite for FPGAs and SoCs. AMD Design Hubs provide links to documentation organized by design tasks and other topics. On the AMD website, see the Design Hubs page.

Figure 1. System-Level Design Flow for FPGAs and SoCs

The following figures show a high-level summary of the design flows for Versal devices. The individual design steps vary based on your design flow and design type as follows:

Traditional design flow for a hardware-only system
Use the traditional design flow. After implementation, proceed to the Hardware Debug step.
Traditional design flow for an embedded system
Use the traditional design flow. After implementation, proceed to the Export Hardware step to add the software stack in the Vitis environment.
Platform-based design flow for an embedded system
Start with the traditional design flow. After implementation, proceed to the Export Hardware step to export the platform to the Vitis environment. Continue with the platform-based design flow. In the Vitis environment, add PL accelerators and the software stack to complete the design.
Platform-based design flow for an embedded AI Engine system
Start with the traditional design flow. After implementation, proceed to the Export Hardware step to export the platform to the Vitis environment. Continue with the platform-based design flow. In the Vitis environment, add PL accelerators, AI Engine accelerators, and the software stack to complete the design.
Figure 2. Traditional Design Flow for Versal Devices

The following figure shows the platform-based design flow through the Vitis environment for Versal devices.

Figure 3. Platform-Based Design Flow for Versal Devices