The C-based High-Level Synthesis (HLS) tools within the Vivado Design Suite enable you to describe various DSP functions in the design using C, C++, and SystemC. You create and validate the C code with the Vivado HLS tools. Use of higher-level languages allows you to abstract algorithmic descriptions, data type, specification, etc. You can create “what-if” scenarios using various parameters to optimize design performance and device area.
HLS lets you simulate the generated RTL directly from its design environment using C-based test benches and simulation. C-to-RTL synthesis transforms the C-based design into an RTL module that can be packaged and implemented as part of a larger RTL design, or instantiated into an IP integrator block design.
The HLS tool flow and features are described in the following resources: