Alternatively, you can choose an in-memory compilation flow in which you manage sources and the design process yourself, known as Non-Project Mode. In-memory compilation enables project settings to be applied to Non-Project based designs. In Non-Project Mode, you manage design sources and the design process yourself using Tcl commands or scripts. The key advantage is that you have full control over each step of the flow.
When working in Non-Project Mode, source files are read from their current locations, such as from a revision control system, and the design is compiled through the flow in memory. You can run each design step individually using Tcl commands. You can also use Tcl commands to set design parameters and implementation options.
You can save design checkpoints and create reports at any stage of the design process. Each implementation step can be tailored to meet specific design challenges, and you can analyze results after each design step. In addition, you can open the Vivado IDE at any point for design analysis and constraints assignment.
In Non-Project Mode, each design step is controlled using Tcl commands. For example:
- If you modify an HDL file after synthesis, you must remember to rerun synthesis to update the in-memory netlist.
- If you want a timing report after routing, you must explicitly generate the timing report when routing completes.
- Design parameters and implementation options are set using Tcl commands and parameters.
- You can save design checkpoints and create reports at any stage of the design process using Tcl.
As the design flow progresses, the representation of the design is retained in memory in the Vivado Design Suite. Non-Project Mode discards the in-memory design after each session and only writes data to disk that you instruct it to. For more information on Non-Project Mode, see Using Non-Project Mode.