Opening a Synthesized Design - 2023.2 English

Vivado Design Suite User Guide: Design Flows Overview (UG892)

Document ID
UG892
Release Date
2023-10-18
Version
2023.2 English

When you open a synthesized design, the Vivado Design Suite opens the synthesized netlist and applies physical and timing constraints against a target part. The different elements of the synthesized design are loaded into memory, and you can analyze and modify these elements as needed to complete the design. You can save updates to the constraints files, netlist, debug cores, and configuration.

In a synthesized design, you can perform many design tasks, including early timing, power, and utilization estimates that can help you determine if your design is converging on desired targets. You can explore the design in a variety of ways using the windows in the Vivado IDE. Objects are always cross-selected in all other windows. You can cross probe to problem lines in the RTL files from various windows, including the Messages, Schematic, Device, Package, and Find windows. The Schematic window allows you to interactively explore the logic interconnect and hierarchy. You can also apply timing constraints and perform further timing analysis. In addition, you can interactively define physical constraints for I/O ports, floorplanning, or design configuration. For more information, see the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).

Using the I/O planning capabilities of the Vivado IDE, you can interactively configure and assign I/O ports in the synthesized design and run DRCs. Select the Run DRC command to invoke a comprehensive set of DRCs to identify logic issues. For more information, see the Vivado Design Suite User Guide: I/O and Clock Planning (UG899) and the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).

You can configure and implement debug core logic in the synthesized design to support test and debug of the programmed device. In the Schematic or Netlist windows, interactively select signals for debug. Debug cores are then configured and inserted into the design. The core logic and interconnect is preserved through synthesis updates of the design when possible. For more information, see this the Vivado Design Suite User Guide: Programming and Debugging (UG908).

To open a synthesized design, use one of the following methods:

  • In the Synthesis section of the Flow Navigator, select Open Synthesized Design.
  • In the Flow Navigator, right-click Synthesis, and select New Synthesized Design from the popup menu.
  • Select Flow > Open Synthesized Design.
  • In the Design Runs view, double-click the run name.

The following figure shows the default view layout for an open synthesized design.

Figure 1. Synthesized Design View Layout