The Xilinx FPGA logic synthesis tools supplied by Synopsys and Mentor Graphics are supported for use with the Vivado Design Suite. In the Vivado Design Suite, you can import the synthesized netlists in structural Verilog or EDIF format for use during implementation. In addition, you can use the constraints (SDC or XDC) output by the logic synthesis tools in the Vivado Design Suite.
All Xilinx IP and Block Designs use Vivado Synthesis. Use of third party synthesis for Xilinx IP or IP integrator block designs is not supported, with a few exceptions, such as the memory IP for 7 series devices. Refer to the data sheet for a specific IP for more information.