Xilinx supports timing simulation in Verilog
only. You can export a netlist for timing simulation from an open synthesized or
implemented design using the command in the Vivado IDE, or by using
The Verilog system task
$sdf_annotate within the simulation netlist
specifies the name of the standard delay format (SDF) file to be read for timing delays.
This directive is added to the exported netlist when the
option is enabled on the Netlist tab of the Simulation Settings dialog box in the
Vivado IDE. The SDF file can be written with the
write_sdf command. The Vivado simulator
automatically reads the SDF file during the compilation step.
Many users do not run timing simulation due to high run time. However, you should consider using full timing simulation because it is the closest method of modeling hardware behavior. If your design does not work on hardware, it is much easier to debug the failure in simulation, as long as you have a timing simulation that can reproduce the failure.
If you decide to skip timing simulation, you should make sure of the following:
- Ensure that your STA constraints are absolutely correct. Pay special attention to exceptions.
- Ensure that your netlist is exactly equivalent to what you intended through your RTL. Pay special attention to any inference-related information provided by the synthesis tool.