Using Non-Project Mode Tcl Commands - 2022.1 English

Vivado Design Suite User Guide: Design Flows Overview (UG892)

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2022.1 English

The following table shows the basic Non-Project Mode Tcl commands. When using Non-Project Mode, the design is compiled using read_verilog, read_vhdl, read_edif, read_ip, read_bd, and read_xdc type commands. The sources are ordered for compilation and passed to synthesis. For information on using the Vivado Design Suite Tcl shell or using batch Tcl scripts, see Working with Tcl.

Note: This document is not a complete reference for the available Tcl commands. Instead, see the Vivado Design Suite Tcl Command Reference Guide (UG835) and Vivado Design Suite User Guide: Using Tcl Scripting (UG894).
Table 1. Basic Non-Project Mode Tcl Commands
Command Description
read_edif Imports an EDIF or NGC netlist file into the Design Source fileset of the current project.
read_verilog Reads the Verilog (.v) and System Verilog (.sv) source files for the Non-Project Mode session.
read_vhdl Reads the VHDL (.vhd or .vhdl) source files for the Non-Project Mode session.
read_ip Reads existing IP (.xci or .xco) project files for the Non-Project Mode session. For Vivado IP (.xci), the design checkpoint (.dcp) synthesized netlist is used to implement the IP if the netlist is in the IP directory. If not, the IP RTL sources are used for synthesis with the rest of the top-level design. The .ngc netlist is used from the .xco IP project.
Note: The .xco file is no longer supported in UltraScale device designs.
read_checkpoint Loads a design checkpoint into the in-memory design.
read_xdc Reads the .sdc or .xdc format constraints source files for the Non-Project Mode session.
read_bd Reads existing IP Integrator block designs (.bd) for the Non-Project session.


Used for multiple purposes. For example, it can be used to define design configuration, tool settings, and so forth.
link_design Compiles the design for synthesis if netlist sources are used for the session.
synth_design Launches Vivado synthesis with the design top module name and target part as arguments.
opt_design Performs high-level design optimization.
power_opt_design Performs intelligent clock gating to reduce overall system power. This is an optional step.
place_design Places the design.
phys_opt_design Performs physical logic optimization to improve timing or routability. This is an optional step.
route_design Routes the design.
report_* Runs a variety of standard reports, which can be run at different stages of the design process.
write_bitstream Generates a bitstream file and runs DRCs.
write_checkpoint Saves the design at any point in the flow. A design checkpoint consists of the netlist and constraints with any optimizations at that point in the flow as well as implementation results.


Opens or closes the Vivado IDE with the current design in memory.