The following table shows the basic Project Mode Tcl commands that control project creation, implementation, and reporting.
|create_project||Creates the Vivado Design Suite project. Arguments include project name and location, design top module name, and target part.|
Adds source files to the project. These include Verilog (.v), VHDL (.vhd or .vhdl), SystemVerilog (.sv), IP and System Generator modules (.xco or .xci), IP Integrator subsystems (.bd), and XDC constraints (.xdc or .sdc).
Individual files can be added, or entire directory trees can be scanned for legal sources and automatically added to the project.
Note: The .xco file is no longer supported in UltraScale device designs.
|set_property||Used for multiple purposes in the Vivado Design Suite. For projects, it can be used to define VHDL libraries for sources, simulation-only sources, target constraints files, tool settings, and so forth.|
|import_files||Imports the specified files into the current file set, effectively adding them into the project infrastructure. It is also used to assign XDC files into constraints sets.|
|Starts either synthesis or implementation and bitstream generation. This command encompasses the individual implementation commands as well as the standard reports generated after the run completes. It is used to launch all of the steps of the synthesis or implementation process in a single command, and to track the tools progress through that process. The -to_step option is used to launch the implementation process, including bitstream generation, in incremental steps.|
|wait_on_run||Ensures the run is complete before processing the next commands in a Tcl script.|
|open_run||Opens either the synthesized design or implemented design for reporting and analysis. A design must be opened before information can be queried using Tcl for reports, analysis, and so forth.|
|close_design||Closes the in-memory design.|
|Opens or closes the Vivado IDE with the current design in memory.|