You can verify Vivado IP by synthesizing the IP and using behavioral or structural logic simulation, and by implementing the IP module to validate timing, power, and resource utilization. Typically, a small example design is used to validate the standalone IP. You can also validate the IP within the context of the top-level design project. Because the IP creates synthesized design checkpoints, this bottom-up verification strategy works well either standalone or within a project.
Many of the Xilinx IP delivered in the Vivado IP
catalog have an example design. You can determine if an IP comes with an example design
by selecting the IP from the IP Sources area of the Manage IP or RTL project and see if
the Open IP Example Design is selectable, as shown in the following figure. This can
also be done using Tcl by examining the
SUPPORTED_TARGETS property of
Use the Open IP Example Design right-click menu command for a selected IP to create an example design to validate the standalone IP within the context of the example design project. For more details on working with example designs and IP output products, refer to the Vivado Design Suite User Guide: Designing with IP (UG896).
Some IP deliver test benches with the example design, which you can use to validate the customized IP functionality. You can run behavioral, post synthesis, or post-implementation simulations. You can run either functional or timing simulations. In order to perform timing/functional simulations you will need to synthesize/implement the example design. For specific information on simulating an IP, refer to the product guide for the IP. For more detail on simulation, refer to the Vivado Design Suite User Guide: Logic Simulation (UG900).