The Timing Constraints window (shown in the following figure) shows the timing constraints used for the loaded design. You can create new constraints, modify existing timing constraints, and run timing reports against the constraints. After the timing constraints are working as desired, you must save the changes to the original constraint set or create a new constraint set to preserve the constraints for the next implementation run. For more information, see this link in the Vivado Design Suite User Guide: Using Constraints (UG903). To open the Timing Constraints window, select , or select Edit Timing Constraints in the Flow Navigator under Synthesized Design or Implemented Design.
Note: To ensure that the report tools recognize the constraint changes, you must press the Apply button in the Timing Constraints window to apply the changes.
Video: Select on a synthesized design to create a top-level XDC file based on design methodologies recommended by Xilinx. This wizard guides you through specifying clocks, setting up input and output constraints, and properly constraining cross-clock domain clock groups. For an overview, see the Vivado Design Suite QuickTake Video: Using the Timing Constraints Wizard.
Figure 1. Timing Constraints Window