Creating a Tcl Checker Procedure - 2022.1 English

Vivado Design Suite User Guide: Using Tcl Scripting (UG894)

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2022.1 English

The Tcl checker procedure selects the design objects of interest to be checked. It then performs the necessary tests or evaluations of the design objects, and finally returns the results in the form of DRC violation objects that identify the objects associated with the specific error.

The following Tcl script defines the dataWidthCheck Tcl checker procedure which checks the width of the WRITE_B bus. This Tcl script file must be loaded into the Vivado tools prior to running the report_drc command. Refer to Loading and Running Tcl Scripts for more information on loading the Tcl checker procedure.

# This is a simplistic check -- report BRAM cells with WRITE_WIDTH_B wider than 36.
proc dataWidthCheck {} {
  # list to hold violations
  set vios {}
  # iterate through the objects to be checked
  foreach bram [get_cells -hier -filter {PRIMITIVE_SUBGROUP == bram}] {
    set bwidth [get_property WRITE_WIDTH_B $bram]
    if { $bwidth > 36} {
      # define the message to report when violations are found
      set msg "On cell %ELG, WRITE_WIDTH_B is $bwidth"
      set vio [ create_drc_violation -name {RAMW-1} -msg $msg $bram ]
      lappend vios $vio
      }; # End IF
    }; # End FOR
    if {[llength $vios] > 0} {
      return -code error $vios
    } else {
      return {}
  }; # End IF
} ; # End PROC

As you can see from the proc definition, the dataWidthCheck procedure accepts no arguments and can find everything it needs from the design. It creates an empty list variable, $vios, to store the violation objects returned by the create_drc_violation command.

The dataWidthCheck procedure iterates through all of the BRAMs in the design, and performs an evaluation of the WRITE_WIDTH_B property on each of those cells. If the WRITE_WIDTH_B of the block RAM cell exceeds a width of 36, a DRC violation is created with a specific message, $msg. The message contains a placeholder for the cell %ELG and the width of the bus found, $bwidth. In the dataWidthCheck procedure, the create_drc_violation command only returns one object, $bram, that maps to the %ELG placeholder defined in the message string. The create_drc_violation command supports messaging placeholders for netlist objects, clock regions, device sites, and package I/O banks by using their respective keys %ELG, %CRG, %SIG, and %PBG.

Important: Both the order and the type of objects passed by create_drc_violation must match the -msg specification in the create_drc_check command, or the expected substitution will not occur.

A violation object is created using the create_drc_violation each time the tested block RAM exceeds the allowable width of the WRITE_WIDTH_B property. The violation object is given the same name as the associated DRC rule in the Vivado Design Suite. It includes the previously defined messaging string, and identifies the specific object or objects that are involved in violation of the rule. The standard object that the design rule violation can return includes cells, ports, pins, nets, clock regions, device sites, and package I/O banks. The message string from the violation can also pass other information, such as the value of a specific property, in order to provide as much detail in the DRC report as needed.

If any violations are found, the dataWidthCheck proc returns an error code to inform the report_drc command of the results of that specific check:

return -code error $vios

In addition to the error code, the violation objects are returned with the $vios variable, which stores a list of violation objects created by the procedure.