- To create new design sources to add to your project, select Note: Alternatively, you can select Add Sources from the right-click menu in the Sources window, or click Add Sources in the Flow Navigator.
- In the Add Sources wizard select Add or Create Design Sources, and click Next.
- In the Add or Create Design
Sources page, press the Create button and select the Create
File command from the sub-menu to create new source files.
- In the Create Source File dialog box,
set the following options, and click OK:
- File type
- Specifies one of the following file formats: Verilog file (.v extension), Verilog Header file (.vh extension), SystemVerilog file (.sv extension), VHDL file (.vhdl or .vhd extension), or Memory file (.mem).
- File name
- Specifies a name for the new HDL source file.
- File location
- Specifies a location in which to create the file.
A placeholder for the file is added to the list of sources displayed in the Sources window. The file is not created until you click Finish in the Add Sources wizard.Tip: You can click Create File multiple times to define several new modules to add to the project.Figure 1. Create Source File Dialog Box
- In the Add or Create Design Sources
page, specify the appropriate library for the source file.Figure 2. Add Sources Wizard—Setting Library
By default, all HDL sources are added to the xil_defaultlib library. In the Library column, you can reference an existing library name, or manually type a new library name to specify additional user VHDL libraries as needed.
- Click Finish to create the new source
files, and add them to the project.
With a new source file created, the Vivado IDE opens the Define Modules dialog box to help you define the ports for the module or entity declaration.
- In the Define Modules
dialog box, you can define the module or entity for the Verilog, Verilog Header,
SystemVerilog, or VHDL code using the following options: Figure 3. Define Modules Dialog Box
- New Source Files
- This field appears if you created multiple files, letting you select the name of the module you want to define.
- Entity name/Module name
- Specifies the name for the entity construct in the
VHDL code or the module name in the Verilog or SystemVerilog
code.Note: The name defaults to the file name but can be changed.
- Architecture name
- Specifies the Architecture for VHDL source files. By
default, the name is Behavioral.Note: This option does not appear when defining Verilog or SystemVerilog modules.
- I/O Port Definitions
- Define the ports to be added to the module definition:
Note: MSB and LSB are ignored if the port is not a bus port.
- Port Name
- Defines the name of the port to appear in the RTL code.
- Specifies whether the port is an Input, Output, or Bidirectional port.
- Specifies whether the port is a bus port. Define the width of the bus using the MSB and LSB options.
- Defines the number of the most significant bit (MSB). This combines with the LSB field to determine the width of the bus being defined.
- Defines the number of the least significant bit (LSB).
The Sources window lists the newly defined modules. To edit the new source files in the Vivado IDE Text Editor, double-click the file or select Open File from the right-click menu. See Using the Text Editor in the Vivado Design Suite User Guide: Using the Vivado IDE (UG893) for information on editing the file.