An RTL project may have RTL, block design, IP and/or RTL sources. This dialog lets you specify which sources to add during project creation. Addition files can be added later during RTL code development, analysis as well as synthesis and implementation. For more information on RTL development and analysis, see Elaborating the RTL Design.
- Follow the steps in Creating a Project.
- In the Project
Type page, select RTL
Project, and click Next.
Note: If necessary, you can select Do not specify sources at this time. This skips the steps of adding design sources and enables you to select the target part and create the project.Note: Extensible platforms are used by Vitis software platform to incorporate software kernels. Setting this project property enables platform properties to add interfaces which can then be augmented by Vitis software platform. For more information on extensible platforms, see Creating Embedded Platforms in Vitis in the Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393).
- In the Add Sources
page, set the following options, and click Next:
- Add Files
- Opens a file browser so you can select files to add
to the project. You can add the following file types to an RTL
project: Verilog, VHDL, SystemVerilog, BD, XCI, EDIF, NGC, BMM, ELF,
and other file types.Note: In the Add Source Files dialog box, each file or directory is represented by an icon indicating it as a file or folder. A small red square indicates it is read only.
- Add Directories
- Opens a directory browser to add source files from the selected directories. Files in the specified directory with valid source file extensions are added to the project.
- Add Sources from Subdirectories
- Specifies that the tool should scan the listed directory's directory tree for additional sources.
- Create File
- Opens the Create Source File dialog box in which you
can create new VHDL, Verilog, Verilog header, or SystemVerilog
files. In the Create Source
File dialog box, set the following options:
Note: A placeholder for the file is added to the list of sources. The file is created when you click Finish.
- File type
- Specifies one of the following file formats: Verilog file (.v extension), Verilog Header file (.vh extension), SystemVerilog file (.sv extension), VHDL file (.vhdl extension), or Memory Files (.mem extension).
- File name
- Specifies a name for the new HDL source file.
- File location
- Specifies a location in which to create the file.
- Specifies the RTL library for a file or directory.
You can select a library name, or specify a new library name by
typing in the Library text field.Note: This option applies to VHDL files only. By default, HDL sources are added to the xil_defaultlib library. You can create or reference additional user VHDL libraries as needed. For Verilog and SystemVerilog files, leave the library set to xil_defaultlib.
- HDL Source for
- Specifies whether the source being loaded is an RTL source file for synthesis and simulation or an RTL test bench for simulation only.
- Removes the selected source files from the list of files to be added.
- Move Up/Move Down
- Moves the file or directory up/down in the list order. The order of the files affects the order of elaboration and compilation during downstream processes such as synthesis and simulation.
- Scan and Add RTL Include Files into Project
- Scans all RTL source files and adds any referenced Verilog 'include files into the project structure.
- Copy Sources into Project
- Copies the added source files and include files into the local project directory instead of referencing the original files. If you added directories of source files using Add Directories, the directory structure is maintained when the files are copied locally into the project. For more information, see Using Remote Sources or Copying Sources into Project.
- Add Sources from Subdirectories
- Adds source files from the subdirectories of directories specified with Add Directories.
- Target Language
- Specifies the target language for the design as either Verilog or VHDL. New RTL files default to the specified target language. Output files are generated from the design in the specified target language.
- Simulator Language
- Specifies the language in which output products are generated for simulation as well as the file types used for third party simulation scripts. For more information, see the Vivado Design Suite User Guide: Logic Simulation (UG900).
- Add Sources
- Invokes a file browser so you can select Xilinx
Core Instance (XCI) files, which are native to the Vivado Design Suite, a Core Container
(XCIX) file, which is a single file representation for an IP, or
CORE Generator core (XCO) files. You can also add Block Design files
(BD) from the Vivado IP
integrator, or Mathworks
files (SLX or MDL) for DSP sub-designs. Figure 1. New Project Wizard—Add Sources Page
The XCI file is an IP-XACT component instance XML file that records the values of project options, customization parameters, and port parameters used to create the IP. The XCIX is a compressed binary file containing the entire IP directory and all output products, including the XCI, synthesis, simulation and support files. See the Core Container section in the Vivado Design Suite User Guide: Designing with IP (UG896) for more details.Note: When you add XCI or XCIX IP created with the Vivado IP catalog, the Vivado IDE automatically imports all available generated targets, such as HDL sources, into the project. When you run synthesis, the IP and the top-level design are synthesized together.
You can also load parameterized cores into the project from within the Vivado IDE using the IP Catalog, as described in Working with IP Sources.
- Optional: In the Add
Constraints page, set the following options, and click
- Add Files
- Invokes a file browser so you can select Synopsys Design Constraint (SDC) or XDC files to add to the project.
- Create File
- Creates a new top-level XDC file for the project.
- Removes the selected file from the constraint list.
- Move Up/Move Down
- Moves a constraint file up or down in the listed order. Commands are order-dependent; the last-read command of a constraint overwrites the effects of an earlier command.
Note: Any SDC or XDC file found in the same directories as the RTL or netlist source files associated with the project are automatically listed as constraint files to be added to the project. You can remove these files as needed.Figure 2. New Project Wizard—Add Constraints Page
- Copy Constraint Files into Project
- Copies constraint files into the local project directory instead of referencing the original files.
- In the Default Part
page, select a Xilinx part or targeted
design platform (TDP) board, and click Next:
Recommended: When you select a board that supports the Vivado Design Suite platform board flow, you can take advantage of automated features in the Vivado IP catalog and Vivado IP integrator. For example, you can automatically create I/O constraints for IP that supports the interfaces available on the selected board. For more information, see Using the Vivado Design Suite Platform Board Flow.Figure 3. New Project Wizard—Default Part Page
- Lists available devices. Information about the
device resources displays in a table view, such as I/O pin count,
the number of look-up tables (LUTs) and flip-flops (FFs), and
available block RAM. You can filter the list using the Product
Category, Family, Sub-Family, Package, Speed Grade, and Temp Grade
filters. You can also use the Search field to find specific
The Vivado Design Suite installation process lets you select which Xilinx devices to install in order to reduce the disk space required by the Vivado tool. If you need to target a part that is not currently installed on your system, you must exit the tool and install the additional parts of interest. Refer to this link in Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973) for more information.
- Lists available development boards, or TDP boards, and the Xilinx part used on the board. Information about device resources displays in a table view similar to the one shown for Parts. You can filter the list using the Vendor, Display Name, and Board Rev filters. You can also use the Search field to find specific board parts.
- In the New Project Summary page, view the selected options that define the project, and click Finish. When you click Finish the project directory structure is created, any files that should be made local to the project are copied, and the project file is written. Any design sources that need to be created must be defined as shown in the following step, and then are written to disk.
- Optional: If you used the Create
File option in step 3, to create a new HDL module and add it to
the project, a Define Module dialog box
appears.Figure 4. Define Module Dialog Box
The RTL source files are created and added to your project. The Sources window lists the newly defined modules. These new source files define the Verilog module or VHDL entity, but you must edit the files to define the logic or architecture for these blocks. To edit the new source files in the Vivado IDE Text Editor, double-click the file or select Open File from the right-click menu. For information on editing the newly created file, see Editing Source Files.