Pin Map - 2022.1 English

Vivado Design Suite User Guide: System-Level Design Entry (UG895)

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2022.1 English

In the <pin_map> section, each physical port is broken down into one or more individual pins. The number of pins in the pin map is determined by the width of the port being mapped. Pins can be shared across different physical ports of the interfaces they are defined in.

Each <pin_map> has a port_index attribute, that maps to an index of the bus port, and a component_pin attribute, that maps to a package pin on the Xilinx device. These are defined as follows:

Table 1. <pin_map> Attributes
Tag Usage/Description Example (KC705)
port_index= Indicates the index of a bus port that is defined in the <port_map>. This is a numeric value within the range defined by the width of port. 3
component_pin= Name of the component pin on the Xilinx device. The component_pin name maps to the name= attribute in the part0_pins.xml file of the FPGA-type <component>. The part0_pins.xml file is located in the same folder as the Board file. GPIO_DIP_SW0

The Pin Map file, commonly named part0_pins.xml, lists the pin names of the Xilinx device, or "fpga" type <component>, and defines the IOSTANDARDs and package pin locations for these component pins. The format of the pins defined in the Pin Map file is as follows:

<part_info part_name="xc7k325tffg900-2">
    <pin index="0" name="GPIO_DIP_SW0" iostandard="LVCMOS25" loc="Y29"/>
    <pin index="1" name="GPIO_DIP_SW1" iostandard="LVCMOS25" loc="W29"/>
    <pin index="2" name="GPIO_DIP_SW2" iostandard="LVCMOS25" loc="AA28"/>
    <pin index="3" name="GPIO_DIP_SW3" iostandard="LVCMOS25" loc="Y28"/>

In the Pin Map file, the following attributes are used to define I/O related constraints for each of the <pins> found on the Xilinx device:

Table 2. Attributes of the Pin Map File
Tag Usage/Description Example (KC705)
index= An index assigned to the <pin> object in the Pin Map file. 0
name= The component pin name on the Xilinx device, used in the Board file. GPIO_DIP_SW2
iostandard= A valid IOSTANDARD for the Xilinx device pin, as defined by the board designer. Valid values include IOSTANDARDs supported by the Vivado Design Suite for the specific component pin. LVCMOS25
loc= The pin location on the Xilinx device package. Y29