Port Map - 2022.1 English

Vivado Design Suite User Guide: System-Level Design Entry (UG895)

Document ID
Release Date
2022.1 English

Each interface is further broken down into individual port maps. These port maps serve as a map of a logical port, that is defined in the interface, with a physical port, that relates to a physical package pin on the Xilinx device.

<port_map logical_port="TRI_I" physical_port="dip_switches_tri_i" dir="in" left="3" 
    <pin_map port_index="0" component_pin="GPIO_DIP_SW0"/>
    <pin_map port_index="1" component_pin="GPIO_DIP_SW1"/>
    <pin_map port_index="2" component_pin="GPIO_DIP_SW2"/>
    <pin_map port_index="3" component_pin="GPIO_DIP_SW3"/>
Table 1. <port_map> Attributes and Tags
Tag Usage/Description Example (KC705)
logical_port= Logical port names are found on the bus interface definition. Predefined interfaces can be found in the Vivado Design Suite installation. For example, the GPIO interface definition is found at: <install_location>\Vivado\ <version>\data\ip\interfaces\ gpio_v1_0 TRI_I

Provides the mapping to port names defined on the board interface in the subsequent section.

physical_port can be a std_logic or std_logic_vector.

dir= Each port has a direction. Allowed values are in, out, and inout. in
left= The high index on the port. For example, a 4-bit bus port [3:0] will be marked as 3. 3
right= The low index for a port. For example, a 4-bit bus port [3:0] will be marked as 0. 0
<pin_maps> Maps the physical port of a Xilinx device to a specific pin of the packaged part. See Pin Map for details and examples.