Working with Vivado HLS Sources - 2022.1 English

Vivado Design Suite User Guide: System-Level Design Entry (UG895)

Document ID
UG895
Release Date
2022-05-11
Version
2022.1 English

The Vivado High-Level Synthesis (HLS) tool transforms a C specification into a register transfer level (RTL) implementation that you can synthesize into a Xilinx device. You can write C specifications in C, C++, or SystemC, and the Xilinx device provides a massively parallel architecture with benefits in performance, cost, and power over traditional processors.

The outputs from Vivado HLS include RTL implementation files in hardware description language (HDL) formats that can be synthesized in Vivado synthesis or packaged as an IP block for use from the IP catalog. For more information, see Vivado Design Suite User Guide: High-Level Synthesis (UG902).