Verification IP can be helpful when performing simulation on designs that are using AXI IP. See the following documents for more information:
- AXI Verification LogiCORE IP Product Guide (PG267)
- AXI4-Stream Verification LogiCORE IP Product Guide (PG277)
- Zynq 7000 SoC Verification IP Data Sheet (DS940)
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Zynq MPSoC UltraScale Verification IP Data Sheet
(DS941) Important: The AXI Verification IP is written in SystemVerilog and uses randomization. Not all third-party simulators support SystemVerilog and randomization. Check Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973) for information about third-party compatibility to the AXI VIP.Video: Also, the following Video is available to help you understand how to use the Zynq 7000 VIP for simulation: Vivado Design Suite QuickTake Video: How to Use the Zynq 7000 Verification IP to Verify and Debug using Simulation.
You can instantiate the IP. If additional Verification IP support for interfaces is required, use one of the following Tcl commands:
set_property CONFIG.INSERT_VIP 1 [get_bd_intf_pin <path_to_interface>]
set_property CONFIG.<interface_name>.INSERT_VIP 1 [get_ips <ipname>]