System Generator automatically compiles designs into low-level representations. The ways in which System Generator compiles a model can vary, and depend on settings in the System Generator token. In addition to producing HDL descriptions of hardware, the tool generates auxiliary files. Some files (e.g., project files, constraints files) assist downstream tools, while others (e.g., VHDL test bench) are used for design verification.
| Compiling and Simulating Using the System Generator Token | Describes how to use the System Generator token to compile designs into equivalent low-level HDL. |
| Compilation Results | Describes the low-level files System Generator produces when HDL Netlist is selected on the System Generator token and Generate is pushed. |
| Vivado Project | Describes the example project System Generator produces when HDL Netlist or IP Catalog is selected on the System Generator token and Generate is pushed. |
| HDL Testbench | Describes the VHDL test bench that System Generator can produce. |