Code generation for a Multiple Clock design supports the following compilation targets:
- HDL Netlist
- IP Catalog
- Synthesized Checkpoint
A screen shot of the top-level hardware is shown in the figure below.
As many clock ports as there are clock domains are exposed at the top level and can be driven by a variety of Xilinx clocking constructs like MMCM, PLL etc. It is assumed that these clocks are completely asynchronous and the following period constraints are created:
These are the only constraints that are required because only FIFO or Dual Port RAM are allowed which have any additional clock domain constraints embedded in the IP.