Configuring the Top-Level System Generator Token - 2020.2 English

Vivado Design Suite User Guide: Model-Based DSP Design Using System Generator (UG897)

Document ID
UG897
Release Date
2020-11-18
Version
2020.2 English

The top-level System Generator token has to be configured to indicate that the Code Generation must proceed for a multiple clock design. This is indicated by turning on the Enable multiple clocks check box in the top-level System Generator token. This indicates to the Code Generation engine that the clock information for the Subsystems src_domain and dest_domain must be obtained from the System Generator tokens contained in those Subsystems. If this check box is not enabled, then the design will be treated as a single clock design where all the clock information is inherited from the top-level System Generator block.

Figure 1. Enable Multiple Clocks